Senior Design Verification Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of experience with Design Verification.
• Experience verifying digital logic at RTL using SystemVerilog and UVM for ASICs.

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• Experience creating and using verification components and environments in a standard verification methodology such as UVM.
• Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
• Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification using Industry leading formal tools.
• Ability to collaborate cross-functionally and globally, fostering relationships and sharing insights to achieve company objectives.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Work with designers, architects and other stakeholders to come up with detailed test plans, coverage plans, dependencies and deliverables.
• Plan the verification of complex Memory Subsystem IPs at IP and Subsystem level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
• Work closely with design, architecture, software, silicon validation, backend implementation stakeholders to make technical decisions.
• Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
• Be the primary point of contact for functional verification of the owned blocks/sub-systems for cross-functional teams.