FPGA Prototyping Applications Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the FPGA world, moving from RTL to synthesis to hardware bring-up, and you know the difference between a design that compiles clean and one that actually meets timing when it hits real silicon. You think from the customer's side of the table because you have been there, wrestling with tools that promise one thing and deliver another, and that perspective shapes how you validate features and write recommendations.

When you see a new synthesis optimization or prototyping flow, your first question is not whether it works in the lab, it is whether it will hold up when someone is three weeks from tapeout with a timing violation they cannot explain. You write test benches that actually stress the corner cases. You debug with Verilog or VHDL fluency that lets you move fast without second-guessing the code.

At Synopsys, you will work on Synplify FPGA synthesis, ProtoCompiler, and Zebu tools that customers depend on to get their designs working. The validation work you do and the application notes you write will directly shape how thousands of engineers experience these tools in the field.

What You'll Be Doing

• Validate new features in Synplify FPGA synthesis, ProtoCompiler, and Zebu from the customer's perspective, not just from the spec sheet
• Analyze quality of results across synthesis runs and propose concrete recommendations to improve timing, area, and power outcomes
• Write test benches in Verilog and VHDL that exercise edge cases, stress tool limits, and catch issues before customers do
• Author application notes and SolvNet articles that help customers understand feature usage, flows, and troubleshooting steps in plain language
• Work closely with R&D teams to translate field findings and validation results into actionable product improvements
• Take ownership of specific feature validation cycles from specification review through release sign-off
• Debug synthesis, back-end flow, and FPGA architecture issues that surface during validation or customer escalations

The Impact You Will Have

• Your validation work will catch tool issues before they reach customers, protecting schedules for teams working under tight tapeout deadlines
• Application notes you write will reduce support load and help customers adopt new features faster and with more confidence
• Recommendations you propose will directly improve QoR metrics that customers measure their success by: timing closure, resource utilization, compile time
• Your customer perspective will shape how new features are designed and documented, making tools more intuitive and reliable in real-world use
• Validation coverage you build will strengthen release quality and reduce post-release patch cycles
• Your technical articles will become go-to resources for field teams and customers troubleshooting complex synthesis and prototyping flows
• The feedback loop you create between validation, R&D, and field engineering will accelerate product maturity and customer satisfaction

What You'll Need

• Bachelor's or Master's in Electronics Engineering, Computer Engineering, or related field
• 5+ years of hands-on experience in logic design and FPGA implementation, from RTL through hardware bring-up
• Strong working knowledge of verification concepts and practical experience writing test benches that catch real issues
• Proficiency in Verilog and VHDL, the kind that lets you read unfamiliar code, spot problems, and write clean testbenches without constant reference checks
• Solid experience with synthesis tools, back-end FPGA flows, and FPGA architecture, you have closed timing on real designs
• Experience with Xilinx or Altera synthesis software is a strong plus
• Scripting ability in Python, Tcl, or Perl is desirable for automating validation and analysis tasks

Who You Are

• You can take a feature spec, think through how a customer will actually use it under pressure, and write a validation plan that covers the cases that matter
• When a synthesis run produces unexpected results, you dig into the RTL, the tool logs, and the architecture until you understand what happened and can explain it clearly
• You write documentation that engineers actually want to read, clear examples, real use cases, no fluff or marketing speak
• You communicate well across teams, you can explain a QoR tradeoff to an R&D engineer and translate a customer complaint into a reproducible test case without losing context
• You stay organized when managing multiple validation streams, feature reviews, and documentation deadlines without dropping threads
• You care about the details, a timing regression that looks small on paper might be a showstopper for someone in the field, and you treat it that way

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.