Functional Verification Engineer

Functional Verification Engineer

Project Role : Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : SoC Verification
Good to have skills : NA
Minimum 5 year(s) of experience is required
Educational Qualification : 15 years full time education

Summary:
As a Functional Verification Engineer, a typical day involves designing and implementing comprehensive testbenches to validate the functional accuracy of digital designs at both block and system levels. The role requires creating various types of tests, including constrained-random, directed, and coverage-driven, to thoroughly assess the design's behavior. Collaboration with design and architecture teams is essential to uncover edge cases and guarantee exhaustive functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication across multiple teams to ensure the highest quality of verification outcomes.

Roles & Responsibilities:
- Expected to be an SME, collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead the development and review of verification plans to ensure alignment with project goals.
- Mentor junior team members to enhance their technical skills and understanding of verification methodologies.
- Coordinate with cross-functional teams to integrate verification efforts and resolve design issues efficiently.

Professional & Technical Skills:
- Must To Have Skills: Proficiency in SoC Verification.
- Strong knowledge of verification methodologies including constrained-random testing and coverage-driven verification.
- Experience with SystemVerilog and Universal Verification Methodology for testbench development.
- Ability to analyze complex digital designs and identify potential corner cases.
- Familiarity with simulation tools and debugging techniques to ensure thorough verification.
- Capability to collaborate effectively with design and architecture teams to enhance verification quality.

Additional Information:
- The candidate should have minimum 5 years of experience in SoC Verification.
- This position is based at our BDC6F - SEZ office.
- A 15 years full time education is required.