Senior Staff Engineer - Analog Design

Sr. Staff Engineer Analog Design

Title: Sr. Staff Engineer, Analog Design

About GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Summary of Role:
We are seeking an experienced Sr. Staff Engineer, Analog Design to work on the design and development of high-performance analog and mixed signal IP. The ideal candidate will play a role in architecture definition, own and drive circuit design, and silicon validation for next generation products. This role requires deep expertise in analog circuit design, strong technical leadership and problem-solving skills, and ability to work cross functionally across global teams including layout, verification, SoC integration and system engineering.

Key Responsibilities:

• Drive design and development of complex analog and mixed signal IP blocks

• Participate and contribute to architecture of analog and mixed-signal IP such as

• Design critical analog blocks such across signal chain and/or power supply blocks as: amplifiers (op-amps, instrumentation amps), comparators, data converters ADC (delta-sigma, SAR, pipeline)/DAC, bandgap references, regulators (DC-DC, LDO) and monitoring circuits like POR, power good, power glitch etc.

• Strong demonstrated design implementation ability to perform transistor-level design using advanced CMOS technology nodes. Perform transistor level schematic circuit design, simulation, and verification using industry standard EDA tools. Strong understanding of analog design fundamentals and technology aspects. Understanding and knowledge of design implementation for robustness covering process variation, mismatch, noise and reliability issues for advanced process nodes

• Perform corner, Monte Carlo functional and reliability analysis to ensure robust performance across silicon PVT comprehending variations

• Drive design reviews, verification strategy, and silicon validation working with different teams across locations. Own and drive deliverables for downstream integration in SoCs

• Cross-collaboration across disciplines working closely with layout engineers for parasitic aware design, verification teams for AMS simulations and product/system teams on architecture and design trade off analysis

• Validation and Characterization skills on post-silicon. Ability to define validation and characterization requirements. Understanding spec compliance requirement needs and drive validation teams. Define architecture to meet Design for Test (DFT) requirements and document bring-up, initialization procedures. Drive design for test cost reductions where applicable 

• Technical leadership in providing technical guidance and mentorship to other junior engineers working in the team. Establish best practices in analog design methodology and verification. Influence roadmap planning for reusable analog IP platforms

• Stay current with the latest trends in semiconductor design, drive design innovations, providing technical leadership and mentoring within the Hardware engineering team. Participate in internal and external technical forums and strive for continuous improvement 

Other Responsibilities:

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

Required Qualifications: 

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field. 

• Minimum 10+ years of experience in analog mixed signal design in end-end design and delivery of complex analog IP blocks. Proven expertise from concept to silicon is required.

• Deep understanding of CMOS analog design fundamentals, noise analysis, stability and compensation, device mismatch and variation. Experience and proven record of meeting power, performance and area requirements. Strong understanding of low-power design techniques required

• Strong knowledge and understanding of industry-standard EDA tools for design and simulation such as Cadence, Synopsys, Ansys etc. Basic scripting and automation using PERL, Python and expertise in virtuoso and analog simulation environments

• Strong analytical and debugging skills: Ability to identify, assess, and aid in debugging complex problems. Proven silicon bring-up and debugging skills required. Familiarity with lab equipment required 

• Excellent communication and documentation skills: Capable of producing clear, comprehensive requirements and architecture and design documentation for both internal and external usage 

• Collaborative mindset: Comfortable working in global, cross-disciplinary teams and engaging directly with different disciplines across design

Preferred Qualifications:

• Experience in ISO 26262/IEC 61508: Experience in applying the standard throughout the development lifecycle, especially at the semiconductor IP and SoC level

• Strong understanding of analog layout techniques

• Driving innovation and participation in industry level technical events, publishing papers/patents is highly preferrable

GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Experience Level

Senior Level