Principal Applications Engineer-Formal Verification

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade building and verifying hardware that cannot afford to fail, and somewhere along the way you stopped accepting "it passes simulation" as good enough. Formal verification is not a side tool for you, it is how you think about correctness, coverage, and the gaps that traditional methods miss. You know the difference between a property that looks right and one that actually proves the behavior, and you have debugged enough counterexamples to spot when the problem is the model, the constraint, or the assumption three layers deep.

Working with customers energizes you. You do not just hand over a tool and a user guide, you sit with their design, understand what keeps their verification lead up at night, and build an environment that actually solves it. You have written enough Tcl, Perl, and Python to automate the repetitive parts so you can focus on the hard thinking. Abstraction techniques, case splitting, invariant development, these are not buzzwords to you, they are moves you make when a proof is stuck and you need to unstick it.

At Synopsys, you will work with some of the most complex designs in the industry and a global team that takes formal verification seriously.

What You'll Be Doing

• Validate VC Formal products by designing RTL blocks, building formal environments, running verification flows, and identifying tool performance bottlenecks or modeling issues
• Work directly with top-tier customers to deploy formal verification methodologies including property verification, sequential equivalence checking, formal coverage, and connectivity checking
• Collaborate with R&D teams to define, specify, and develop next-generation formal verification features and applications based on real customer needs and design challenges
• Diagnose root causes of verification complexity, optimize formal testbenches and constraints, and apply abstraction techniques like cut-points, symmetry, and datapath reduction to improve proof convergence
• Develop automation scripts in Tcl, Perl, and Python to streamline formal flows, improve usability, and scale verification across large design hierarchies
• Manage verification responsibilities for customer engagements, acting as a technical consultant and trusted advisor on formal methodology deployment
• Evaluate and integrate AI agents into formal verification workflows where applicable, exploring new approaches to proof automation and coverage closure

The Impact You Will Have

• Enable customers to catch critical design bugs that simulation would miss, reducing costly respins and time to market
• Shape the roadmap of VC Formal tools by translating real-world customer pain points into actionable product requirements for R&D
• Build reusable formal environments and methodologies that become reference models for customer adoption across industries
• Accelerate formal verification deployment at customer sites, turning skepticism into adoption through clear results and technical credibility
• Drive tool performance improvements by identifying and resolving bottlenecks in proof engines, abstraction layers, and constraint modeling
• Mentor junior engineers and CAE teams globally, raising the technical bar for how formal verification is applied across Synopsys
• Contribute to the evolution of formal verification in an era where AI, complex SoCs, and safety-critical designs demand higher assurance than ever before

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering from a recognized institution, advanced degrees preferred
• 12+ years of hands-on experience in RTL design or verification with a strong focus on formal verification methodologies
• Deep understanding of hardware design languages including Verilog and VHDL, and the ability to read, write, and debug complex RTL
• Strong proficiency in Unix/Linux environments with scripting expertise in Tcl, Perl, and Python for automation and flow development
• Solid grasp of formal verification theory including formal methods, algorithms, complexity theory, and abstraction techniques such as cut-points, symmetry, and datapath abstraction
• Working knowledge of industry-standard bus protocols such as AHB, AXI, or CHI, practical experience with AI agents in formal flows is a plus
• Excellent written and verbal communication skills with the ability to present technical concepts clearly to customers, R&D, and cross-functional teams

Who You Are

• You can walk into a customer meeting, listen to a verification challenge, and sketch out a formal approach on a whiteboard that makes sense to both the design lead and the tool user
• You are comfortable working autonomously, you do not wait for perfect instructions or fully baked requirements, you figure out what needs to happen and make it happen
• When a formal proof fails, you do not give up or blame the tool, you dig into the trace, question the assumptions, and iterate until you understand what is actually going on
• You have managed verification responsibilities before, whether that means owning a block, leading a customer engagement, or consulting across multiple projects, and you know how to keep things moving
• You stay current, you read papers, try new techniques, and think about how emerging methods like AI-assisted verification might change the game, even if the answers are not clear yet
• You can explain a complex formal concept, like invariant strengthening or abstraction refinement, to someone who has never used formal before and have them actually understand why it matters

The Team You'll Be Part Of

You will join the VC Formal Applications Engineering team in Bangalore, a global group that works closely with top customers and R&D to ensure the quality and adoption of Synopsys formal verification solutions. The team is agile, technically deep, and operates in a results-oriented environment where your work directly influences product direction and customer success. Your recruiter will share more about team structure, current projects, and growth opportunities during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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