Physical Design Engineer - Silicon Chip Implementation

Physical Design and Implementation Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience with physical design (e.g., from RTL to GDSII, including key stages like synthesis, floorplanning, place and route, and timing closure).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with scripting languages such as Perl, Python, or Tcl.
  
• Experience with constraints, synthesis or clock tree synthesis (CTS)
  

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Physical Design Engineer, you will collaborate closely with functional design, Design for Testing (DFT), architecture, and packaging engineers.

In this role, you will solve technical problems with innovative, micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Use analytical and simulation techniques to ensure performance, power, and area (PPA) is within defined requirements.
  
• Collaborate with cross-functional teams to debug failures or performance shortfalls program goals in lab or simulation.
  
• Design chips, chip-subsystems, or partitions within subsystems from synthesis through place, route and sign off convergence, ensure that the design meets the architecture goals of power, performance, and area.
  
• Develop, validate, and improve electronic design automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.
  

Experience Level

Mid Level