System on Chip (SoC) Physical Design and Timing Engineer

SoC Physical Design Timing Engineer

Job Details:

Job Description: 

In this job the Candidate shall be responsible for the description below : - Responsible for STA and timing closure activities of Intel SoCs/Partitions. Your tasks may include but not limited to Understanding of Design, Architecture and Clocking, Interaction with FE/DFT/Verification teams, Writing constraints, understanding synchronous - asynchronous paths, Clock domain crossing issues, Timing closure, Generating timing ECOs Timing signoff - Debugging/troubleshooting of timing issues in a design. Additional skills include: - Hands-On experience with domain relevant industry standard tools like Primetime Etc. - Good understanding and exposure of overall SoC Cycle. - Good scripting skills in TCL/Perl/Shell to automate tool/flow methodologies. - You must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. - You shall be self-motivated with the initiative to seek constant improvements and driving new methodologies in the domain expertise. Additional skills include: - Hands-On experience with domain relevant industry standard tools like Primetime Etc. - Good understanding and exposure of overall SoC Cycle. - Good scripting skills in TCL/Perl/Shell to automate tool/flow methodologies. - You must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. - You shall be self-motivated with the initiative to seek constant improvements and driving new methodologies in the domain expertise.

Qualifications:

Qualifications and Experience You must possess a Bachelor of Engineering degree or Master of Engineering in Electrical and/or Electronics Engineering with 10+ Years of relevant experience with the skills in Physical Implementation and Timing Closure.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Experience Level

Senior Level