Mixed Signal IP CAD and Methodology Lead - ASIC Development Engineering

Technologist, ASIC Development Engineering (Mixed Signal IP CAD/Methodology Lead)

Company Description

SanDisk is uniquely positioned at the heart of the AI-driven data economy, with a focused portfolio centered on advanced NAND flash and SSD technologies that underpin cloud, enterprise, and hyperscale infrastructures. As AI workloads continue to explode in scale and complexity, the need for high-throughput, low-latency, and energy-efficient storage has become mission-critical—an area where SanDisk’s technology leadership clearly stands out.

Now operating as a focused, independent storage company, SanDisk has sharpened its execution and innovation engine to serve the rapidly growing AI, data center, and edge markets. Its inclusion in the S&P 500 is a strong validation of both its operational maturity and its relevance as a core infrastructure player in the global technology ecosystem.

 As AI increasingly moves from training to large-scale inferencing, storage plays a decisive role in system performance. Fast access to models, embeddings, and real-time data requires ultra-low latency, high endurance, and power-efficient storage—particularly in distributed and edge deployments. SanDisk’s flash-based solutions are well aligned to enable efficient, scalable AI inferencing by minimizing data movement bottlenecks between compute and storage.

Driven by experienced leadership and a clear long-term vision, SanDisk is not just responding to the AI wave—it is helping define the storage foundation on which next-generation AI systems will be built.

Job Description

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-class NAND Flash products used globally at massive scale. Design Enablement team enables the Technology, Methodology and Flows to the Mixed Signal IP team to deliver best in class products. As the MSIP CAD/Methodology Lead, you will play a pivotal role in defining, architecting, and delivering robust MSIP Design methodologies on cutting-edge technology nodes, enabling best-in-class quality and productivity.

This role is ideal for a seasoned  MSIP methodology leader who enjoys solving complex cross-domain problems, working closely with foundries, and driving innovation across flows, tools, and teams.

Key Responsibilities

• Lead mixed-signal IP CAD and methodology development, covering schematic, layout, verification, and signoff flows.

• Architect and maintain end-to-end custom design methodologies, from transistor-level design through signoff-ready layouts.

• Drive layout quality standards, including matching, symmetry, parasitic control, reliability, and manufacturability.

• Define and enforce physical verification methodologies, including:

  • DRC

  • LVS

  • PERC

  • Reliability and signoff checks

• Own and evolve signoff methodologies for mixed-signal IPs, including EM/IR analysis and reliability verification.

• Work closely with custom circuit designers and layout teams to identify recurring issues and introduce automation, checks, and best practices.

• Collaborate with foundry counterparts to understand process-specific constraints, reliability requirements, and rule interpretations.

• Develop correct-by-construction and shift-left flows to catch issues early and reduce iteration cycles.

• Drive tool qualification, flow robustness, and productivity improvements across multiple IP programs.

• Mentor engineers and foster a culture of quality, rigor, and innovation within the CAD/methodology team.

Qualifications

Requirements

• 10+ years of experience in mixed-signal / analog design, custom layout, CAD, or methodology roles.

• Strong understanding of transistor-level circuit design, including device behavior, biasing, matching, noise, and variability.

• Hands-on experience with custom layout design and a deep appreciation of layout quality and its impact on circuit performance.

• Expertise in physical verification and signoff, including:

  • DRC, LVS, PERC

  • EM/IR and reliability signoff tools

• Proven experience architecting custom design and verification methodologies for mixed-signal IPs.

• Strong understanding of interactions between circuit design, layout parasitics, and signoff requirements.

• Proficiency in scripting and automation using SVRF, SKILL, TCL, Python, and/or Perl.

• M.Tech / MS in VLSI Design, Microelectronics, or a related field (or equivalent industry experience).

Additional Information

Desirable Skills

• Exposure to advanced nodes  and complex signoff requirements.

• Experience with memory controllers or high-performance data-path designs.

• Prior experience applying AI/ML in EDA or design automation is a strong plus.

• Strong communication and stakeholder management skills.

Experience Level

Senior Level