PCIe Lead Engineer - Embedded Linux Platform

PCIe Lead Engineer

PCIe Lead Engineer – Linux Enablement & AVV (Pre/Post-Silicon) – RISC‑V MPU Platform 

Location: Pune / Bangalore, India 

Own PCIe bring-up on Linux - Root Complex/Endpoint enablement, performance, and AVV from FPGA to first silicon. 

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries make possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Introduction:

We’re building a next-generation, application-class RISC‑V MPU SoC platform for Linux systems - bringing together multimedia, industrial connectivity, security, and high-speed I/O. 

In the Platform Software team, you will be the technical owner for PCIe across the stack: boot-to-user-space enablement, Linux kernel/driver integration, and automated validation (AVV) on virtual platforms/FPGA and first silicon. You’ll partner closely with architects and hardware teams to de-risk the PCIe subsystem, drive bring-up readiness, and deliver a production-quality SDK experience. 

Key Responsibilities 

• PCIe Linux enablement & integration: enable and maintain PCIe Root Complex and/or Endpoint functionality on a 64-bit RISC‑V MPU Linux platform. 

• Bring up the PCIe controller, PHY/SerDes integration, clocks/resets, link training (LTSSM), and interrupt routing. 

• Drive kernel/BSP enablement: Device Tree bindings, address translation/windows, IOMMU interactions (where applicable), and power management (ASPM, suspend/resume). 

• Own PCIe functionality in Linux: enumeration, configuration space, BAR programming, DMA engines, and interrupt mechanisms (legacy/MSI/MSI‑X). 

• Enable and validate reliability features: link up/down recovery, error handling (AER), timeouts, and robustness across hot reset and stress scenarios. 

• Deliver PCIe-ready SDK releases: integration, regression validation, and developer-facing documentation/debug guides (e.g., lspci workflows, link/debug playbooks). 

• AVV & silicon validation (pre/post-silicon): create test plans and automation to validate PCIe functionality, performance, and interoperability on FPGA/emulation and first silicon. 

• Contribute to shift-left validation using virtual platforms/emulation/FPGA; build reusable PCIe validation tests for link bring-up, enumeration, DMA throughput, and error injection. 

• Debug and root-cause PCIe issues across HW/FW/kernel using logs, traces, and lab equipment (e.g., JTAG, protocol analyzers/exercisers, oscilloscopes/BERT where applicable); drive fixes to closure. 

• Cross-functional ownership: partner with architects, RTL/SerDes/PHY, board, and platform teams to define requirements, de-risk schedules, and land PCIe features. 

• Own PCIe feature planning: lane/width/speed targets (Gen2/Gen3/Gen4 as applicable), RC/EP mode requirements, reset/clocking, and bring-up milestones. 

• Provide bring-up and validation feedback that influences PCIe architecture decisions (debug hooks/observability, compliance testability, error reporting, and recovery behavior). 

• Align with internal and external stakeholders on deliverables, bug triage, and release readiness for PCIe enablement. 

• Customer & ecosystem engagement: support early adopters and upstream fixes when appropriate (kernel, Device Tree, PCI subsystem/endpoint framework). 

• Work with OEMs/Tier‑1s during bring-up and PCIe interoperability (different endpoints/switches); contribute patches upstream when it improves maintainability. 

Required Qualifications 

• B.E./B.Tech or M.E./M.Tech in Computer Engineering, Electrical Engineering, or a related field. 

• Strong experience  with minimum 8-12 years in Embedded Linux platform/BSP and device-driver development. 

• Expert-level C programming; comfortable reading and modifying kernel, driver, and low-level firmware code. 

• Strong Linux internals knowledge: boot flow, memory/interrupt subsystems, concurrency, and performance debugging. 

• Hands-on SoC/platform bring-up experience, including high-speed I/O enablement and ownership mindset for subsystem quality. 

• Hands-on with U‑Boot, Linux kernel, Device Tree, and Yocto/OpenEmbedded; experience integrating and validating PCIe in BSP/SDK releases. 

• Strong debugging skills with GDB and at least one of OpenOCD/JTAG, Lauterbach, or similar tools; able to debug complex HW/SW interactions. 

• Experience working on FPGA, emulation, or early-silicon platforms for bring-up/validation. 

Good to Have 

• Deep PCIe knowledge and familiarity with Linux PCI subsystem (Root Complex and Endpoint concepts, enumeration/config space, AER). 

• Experience with PCIe compliance/interoperability testing and post-silicon triage (link training/LTSSM, equalization, error injection, throughput). 

• Exposure to advanced PCIe features such as SR‑IOV, ATS/PRI, hot-plug/hot reset, and PCIe switches is a plus. 

• Familiarity with platform security boundaries relevant to PCIe (DMA attack surface, IOMMU/SMMU concepts, secure boot boundaries). 

• Experience with QEMU, virtual platforms, or emulation workflows used for early driver/test development (including PCIe RC/EP scenarios where applicable). 

• Exposure to CI/CD and automated validation (Python/shell test frameworks, dashboards, regressions) for continuous PCIe quality. 

What We Offer 

• Build a RISC‑V MPU platform from the ground up and see it shipped in real products. 

• End-to-end ownership across pre-silicon → FPGA → first silicon → production SDK releases. 

• Work closely with CPU architects and SoC teams; your data drives decisions. 

• Deep technical work, strong peer group, and long-term growth on a strategic platform 

More about us:

MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.

MIPS - GlobalFoundries company is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

 

Experience Level

Senior Level