R&D Engineering, Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building RTL that ships in silicon, not just passes simulation. You know that the real work begins when you integrate five IP blocks into a subsystem and discover that three of them assume mutually exclusive clock strategies. You have debugged enough CDC violations at 2 a.m. to know which ones matter and which ones are tool noise, and you can tell the difference in about thirty seconds.

Architecture documents do not intimidate you. You read them, ask the clarifying questions no one else thought to ask, and then build something that actually matches the intent, not just the letter. When synthesis fails at 87% because of a constraint you wrote three weeks ago, you do not panic. You open the log, trace it back, fix it, and move on.

You have written enough SDC to know that constraints are half art, half science, and entirely about understanding what the downstream tools actually need. Glue logic does not scare you. Neither does owning an entire block from microarchitecture through post-synthesis handoff. At Synopsys, you will work on SoC designs that power real products, alongside engineers who care as much about the details as you do.

What You'll Be Doing

• Design and develop RTL using Verilog and SystemVerilog for complex SoC and ASIC components that go into production silicon
• Integrate IP blocks at the SoC level, building the glue logic and subsystem architecture that makes everything actually work together
• Write SDC for synthesis, ensuring your constraints reflect the real timing intent and do not create downstream surprises
• Run and debug lint, CDC, and synthesis checks using tools like SpyGlass, Fusion Compiler, and Encounter, resolving issues before they become integration blockers
• Collaborate with verification, physical design, and architecture teams to close functional and structural issues across the design cycle
• Contribute to microarchitecture discussions and translate architectural intent into working RTL that meets performance, power, and area targets
• Mentor junior engineers on RTL quality, coding standards, and front-end design best practices when the opportunity arises

The Impact You Will Have

• Your RTL integration work directly enables complex SoCs to move from architecture to physical implementation without costly respins
• The synthesis constraints you write determine whether the design meets timing on the first pass or requires weeks of iteration
• Your ability to debug CDC and lint issues early prevents verification and physical design teams from hitting walls later in the schedule
• The glue logic and subsystem designs you build become the connective tissue that makes multi-IP integration actually function
• Your technical guidance helps junior engineers avoid common pitfalls and build higher-quality RTL from the start
• The blocks you own and deliver on schedule keep entire project timelines on track
• Your collaboration across teams ensures that architectural intent, RTL implementation, and physical constraints stay aligned throughout the design cycle

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field with a minimum of 5 years of related experience, or a Master’s degree with 3 years of relevant experience.
• Hands-on experience in RTL design and SoC or ASIC integration, with a track record of owning blocks through synthesis
• Strong proficiency in Verilog and SystemVerilog for production RTL development
• Solid understanding of digital design fundamentals, microarchitecture, and SoC integration challenges
• Experience running lint tools like SpyGlass or Leda, CDC analysis tools, and synthesis flows using Fusion Compiler or Encounter
• Ability to write SDC and debug synthesis issues in complex, multi-clock designs

• Experience with high-speed interfaces like PCIe, USB, AXI, I2C, or JTAG is a strong plus, as is familiarity with low-power design techniques and scripting in Python, Tcl, or Perl 

Who You Are

• You can look at a 10,000-line RTL module and spot the structural issue that is going to cause a synthesis problem three steps downstream
• You do not wait for perfect specs. You read what is available, flag the gaps, and start building while the architecture team fills in the details
• When a CDC violation shows up in a report, you can quickly determine whether it is a real cross-domain hazard or a false positive from an overly conservative tool setting
• You communicate clearly with people who do not speak RTL. You can explain a clock domain crossing issue to a verification engineer or a constraint tradeoff to a physical design lead without losing the technical thread
• You take ownership. If a block is yours, you see it through lint, CDC, synthesis, and handoff, and you do not consider it done until the next team can actually use it
• You are comfortable mentoring others, not because you have all the answers, but because you know how to help someone work through a problem without just giving them the solution

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#TPG

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.