ASIC Design Verification Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 Years of experience verifying digital logic at RTL level using SystemVerilog or C/C++.
• Experience creating and using verification components and environments in standard verification methodology.
• Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in low-power design verification.
• Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
• Experience in one or more of the following: Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock and Power Controllers.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As an ASIC Design Verification Engineer, you will be part of a Research and Development team, and your responsibilities will include building verification components, constrained-random testing, system testing, and verification closure.

Responsibilities

• Work cross-functionally to debug failures and verify the functional correctness of the design.
• Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.
• Plan and execute the verification of the next generation configurable Infrastructure IPs, interconnects and memory subsystems.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Close coverage measures to identify verification holes and to show progress towards tape-out.