Synopsys India Pvt Ltd

IP Design Technical Lead/ Staff ASIC RTL Design Engineer

Synopsys India Pvt Ltd
Bengaluru/Bangalore
Not disclosed
Work from OfficeWork from Office
Full TimeFull Time
Min. 5 yearsMin. 5 years

Job Description

IP Design Technical Lead/ Staff ASIC RTL Design Engineer

General Information

Job Title
IP Design Technical Lead/ Staff ASIC RTL Design Engineer
Job ID
16586
Country
India
City
Bengaluru
Date Posted
24-Mar-2026
Job Category
Engineering
Job Subcategory
ASIC Digital Design
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements

Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable the semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security. 

LPDDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of LPDDR PHY IP products.  All current and next-generation technologies are being developed by the LPDDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.

We are looking for Staff ASIC Digital Verification Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare LPDDR PHY IP solution. Be part of a global diverse team that pushes boundaries on LPDDR PHY IP development and solution, your passion and expertise will shape the next generation of product innovation, performance, and efficiency.

 


Job Description

    Defining and tracking Verification test plans

    Designing and writing constrained-random SystemVerilog testbenches using UVM

    Writing SystemVerilog assertions

    Writing functional coverage

    Debugging RTL and GLS failures

    Code coverage Analysis

    Providing mentoring and guidance to less experienced team members


Required Skills

    BSEE in EE with 5+ years of industry experience

    Digital verification in UVM environment Formal Verification is a plus

    Understanding of memory and memory PHY architecture

    Knowledge of DFI, Memory Controller or Memory Subsystem

    Verilog, System Verilog and Perl/Python scripting skills

    Debugging skills 

    Demonstrates good communication and problem-solving skills

    Understanding of high-speed interface protocols is a plus


At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Experience Level

Senior Level

Job role

Work location
Work locationBengaluru, India
Department
DepartmentProduction / Manufacturing / Engineering
Role / Category
Role / CategoryManufacturing R&D
Employment type
Employment typeFull Time
Shift
ShiftDay Shift

Job requirements

Experience
ExperienceMin. 5 years

About company

Name
NameSynopsys India Pvt Ltd
Job posted by Synopsys India Pvt Ltd

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Senior ASIC RTL Design Engineer - IP Design Technical Lead in Synopsys India Pvt Ltd | apna.co