Senior Design Verification Engineer

Senior Design Verification Engineer

Job Details:

Job Description: 

The Role and Impact Join Intel as an IP Design Verification Engineer for the Silicon Chassis team and play a critical role in shaping the future of cutting-edge technology. In this role, you will contribute to the development and verification of Intellectual Property (IP) logic, ensuring that our designs meet rigorous specifications and exceed industry standards. As a key member of the design verification team, you will collaborate with architects, RTL developers, and physical design teams to validate complex features and create robust, high-quality products. Your work will directly impact Intel's ability to deliver innovative solutions that power the world's most advanced computing systems. Key Responsibilities - Develop and execute detailed verification plans to confirm IP logic adheres to microarchitecture specifications. - Create and maintain test benches and verification environments using best-in-class methodologies such as OVM and UVM. - Perform functional and system-level simulations to identify and debug issues, ensuring coverage and compliance with requirements. - Root cause failing tests and implement corrective measures to resolve design issues. - Collaborate with cross-functional teams to improve verification strategies and ensure optimal integration of complex architectural and microarchitectural features. - Analyze power and timing impacts during verification to support overall design optimization. - Document verification plans, methodologies, and results, and lead technical reviews to refine and enhance verification frameworks. - Maintain and enhance existing verification infrastructure, contributing to the evolution of methodologies and tool flows.

Qualifications:

Minimum Qualifications - Proficiency in hardware simulation, SystemVerilog, and advanced verification methodologies such as OVM and UVM. - Strong expertise in developing and executing IP test plans and creating detailed verification environments. - Solid understanding of interconnect and bus protocols such as AMBA AXI/ACE/CHI, PCIe, or CXL, and working knowledge of cache coherency concepts. - Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. - 4+ years of experience with a Bachelor's degree, or 3+ years with a Master's degree, focusing on IP-level design verification. Preferred Qualifications - Experience with Design for Verification (DFV) techniques and methodologies. - Demonstrated ability to drive technical reviews and collaborate effectively with architects and design teams. - Familiarity with emerging trends in verification technologies and a passion for innovation in the field. Intel is committed to fostering a culture of innovation, inclusion, and excellence. If you are excited about solving complex technical challenges and making a lasting impact, we encourage you to apply and be part of our journey to shape the future of technology.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.