Functional Verification Engineer

Functional Verification Engineer

Project Role : Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : SoC Verification
Good to have skills : NA
Minimum 7.5 year(s) of experience is required
Educational Qualification : 15 years full time education

Summary:
As a Functional Verification Engineer, a typical day involves designing and implementing comprehensive test environments to ensure the accuracy and reliability of digital hardware designs. This role requires close collaboration with various teams to identify potential edge cases and verify that all functional aspects of the design meet the required specifications. The engineer continuously refines testing strategies to achieve thorough coverage and supports the project through all stages leading up to tape-out, ensuring the product's readiness for production. The work environment is dynamic, involving problem-solving and iterative improvements to verification processes.

Roles & Responsibilities:
- Expected to be an SME, collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead the development and maintenance of verification plans and testbenches to ensure comprehensive functional coverage.
- Mentor junior team members by providing guidance and support in verification methodologies and best practices.
- Coordinate cross-functional reviews to align verification goals with design and architecture requirements.

Professional & Technical Skills:
- Must To Have Skills: Proficiency in SoC Verification.
- Strong knowledge of verification methodologies including constrained-random testing, directed testing, and coverage-driven verification.
- Experience with hardware description and verification languages such as SystemVerilog and Universal Verification Methodology.
- Ability to develop and debug complex testbenches and simulation environments.
- Familiarity with functional coverage metrics and coverage closure techniques.
- Skilled in collaborating with design and architecture teams to identify and address corner cases.

Additional Information:
- The candidate should have minimum 7.5 years of experience in SoC Verification.
- This position is based at our Bengaluru office.
- A 15 years full time education is required.