Senior ASIC RTL Integration Engineer

ASIC RTL Engineer, Integration

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital reasoning design principles, RTL design concepts, and languages like Verilog or SystemVerilog.
• Experience with micro-architecture and coding in one or more of these areas: memory compression, interconnects, coherence, cache, Dynamic Random Access Memory (DRAM) controller, Physical Layer Devices (PHYs).
• Experience in performance design, multi power domains with clocking.
• Experience with multiple System on a chip (SoCs).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with micro-architecture design, with the knowledge of system design to develop IPs with PPA.
• Experience with multiple quality checks performed at front-end (e.g., Lint, CDC/RDC, Synthesis, LEC, etc.).
• Experience with chip design flow, with the knowledge of cross-domain involving Design Verification (DV)/Design for Testability (DFT)/Physical Design/Software.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Work on a team of Register-Transfer Level (RTL) engineers with Internet Protocol (IP)/Subsystem development. Plan tasks, build subsystems, run quality flows, create automation, hold code and design reviews, code development of features in the IP/Subsystem.
• Interact with the architecture team and develop implementation (e.g., micro-architecture and coding) strategies to meet quality, schedule and Power Performance Area (PPA) for the IP.
• Work with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Experience Level

Senior Level