Design for Test (DFT) Lead Engineer

DFT Lead (Scan/ATPG) Engineer

Job Details:

Job Description: 

• You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. • As a DFT engineer direct responsibilities of the role, but not limited to, working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG. • The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc. • Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus

Qualifications:

• Candidate must possess a Master's degree in Electronics or Computer Engineering with at least 7 or more years of experience or a bachelor's degree with at least 9 years of experience in DFT. • Strong knowledge of ATPG, various fault models, fault grading. • Knowledge of memory BIST, IJTAG/TAP architecture. • DFT logic generation, integration, and verification. • EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring uppreferably. • Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug. • Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer. • Post Silicon/ATE Bring-Up Support. • Experience with RTL (Verilog, System Verilog, VHDL)

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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