Formal Verification Engineer

Do Something Wonderful! 

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. 

Who We Are 

The DCAI and Silicon Eng Team (DASE) deliver leadership Xeon products to cloud and datacenter customers through development of industry leading IPs that enhances product performance and competitiveness in both Xeon and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building blocks for the Xeon server SOCs. 

Who You Are 

Come and join a winning team at FVCTO (Formal Verification Central Tech Office). As a Formal Verification Engineer, you will be responsible the following but not limited to: 

• Verify microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs & SOCs for Server, Client and Graphics. 

• Use the hardware architecture design and RTL implementation details. 

• Define the Formal Verification scope, deploy the right strategy to prove the correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design. 

• Carve out the right boundaries for the design, create comprehensive formal verification test plans, track, verify, apply abstraction techniques, and converge on complex designs to deliver a high-quality design on schedule and articulate the ROI. Analyses new methodologies, evaluates new tools and corroborates results. 

• Work with vendors on resolving hard design and tool problems. 

In addition to the qualifications a successful candidate will demonstrate: 

• Problem solving and debugging skills. 

• Willingness to work closely with various design teams and cross site teams. 

• Verbal and written communication skills. 

• Motivated, self-directed and can work effectively both independently and in a team environment. 

Minimum Qualifications 

The candidate must possess the following; 

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 8 years relevant experience or schoolwork 

• – OR - Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 7 years relevant experience  or schoolwork 

•  – OR – PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field with 3 year relevant experience or schoolwork 

Experience in the following: 

• RTL languages like System Verilog or VHDL 

• Assertion languages like SVA, formal verification. 

Preferred Qualifications 

Experience with: 

• The fundamentals of formal verification technology, including model checking and writing formal assertions to express architectural intent of designs 

• Formal verification principles and methods 

• Computer architecture, digital design and verification methods 

• Research in formal verification domain