RTL Design Engineer - ASIC and Microarchitecture

RTL Design Engineer, Silicon Engineering, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 1 year of experience in ASIC development with Verilog/SystemVerilog, VHSIC Hardware Description Language (VHDL), or Chisel.
• Experience in ASIC design verification, synthesis, timing/power analysis, and design for testing (DFT).
• Experience in micro-architecture and design of IPs and subsystems.

Preferred qualifications:

• Experience with scripting languages (e.g., Python or Perl).
• Experience in system on a chip (SoC) designs and integration flows.
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Knowledge of high performance and low power design techniques.

About the job

Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.

In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next-generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions and evaluate design options with performance, power and area.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Own microarchitecture and implementation of Internet Protocols (IPs) and subsystems.
• Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications.
• Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) and Physical Design (PD) teams.
• Identify and drive power, performance and area improvements.

Experience Level

Mid Level