Register Transfer Level (RTL) Design Engineer

RTL Engineer, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• 3 years of experience in ASIC design flows and methodologies, IP integration (subsystems, memories, IO's and analog IP) and RTL design.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
• Experience in the semiconductor industry, with experience in emulation or FPGA prototyping.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience in a scripting language like Perl or Python.
• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.
• Participate in test plan and coverage analysis of the block and ASIC-level verification.
• Modify ASIC Register-Transfer Level (RTL) for a given IP/subsytem to a dedicated FPGA prototyping platform.
• Run the end-to-end FPGA flow (including synthesis, place and route, timing) for an IP/subsystem.
• Develop the necessary collaterals (tests, porting scripts) to bring-up the IP/subsystem on the FPGA platform.

Experience Level

Mid Level