Senior ASIC RTL Integration Engineer

Senior ASIC RTL Integration Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• 8 years of experience with multiple IPs/SoCs with silicon success.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with a scripting language like Perl or Python.
• Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
• Knowledge of memory compression, fabric, coherence, cache, or DRAM.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
• Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
• Participate in test plan and coverage analysis of the block and ASIC-level verification.
• Communicate and work with multi-disciplined and multi-site teams.

Experience Level

Senior Level