Senior CPU Design Engineer - Front-End Integration and Flow

Senior CPU Design Engineer- FE Integration and FE Flow

Job Details:

Job Description: 

The person will lead sophisticated front-end integration projects and quality assurance initiatives across BDC, IDC, and US teams. This senior role involves driving complex subIP integration activities, providing expert-level static methodology sign-off, and ensuring comprehensive design quality through advanced analysis techniques. Will lead complex subIP integration activities and serve as an expert in static methodology sign-off processes. This senior role requires deep expertise in front-end integration methodologies, advanced static analysis techniques, and comprehensive quality assurance practices. The candidate will drive end-to-end integration workflows, mentor junior team members, and ensure design quality through expert-level application of CDC, RDC, Lint, and low-power static sign-off methodologies. This position demands strong technical leadership, cross-functional collaboration skills, and the ability to resolve complex integration challenges across multiple Intel development sites.

Qualifications:

The ideal candidate should have experience in many or all the following • Minimum of 7 years of work experience, Should have experience in end-to-end subIP integration activities for complex CPU designs across multiple sites • Provide expert-level static sign-off including CDC, RDC, Lint, and VC-LP methodologies • Drive quality assurance processes and establish design quality metrics and standards along with developing and optimize integration flows and methodologies for improved efficiency. • Mentor team members and engineers and provide technical guidance on integration best practices • Collaborate with teams to ensure seamless integration. Resolve complex integration challenges and debug sophisticated design issues. • Lead cross-site technical discussions and drive consensus on integration approaches. Interface with vendor partners to resolve advanced tool issues and drive enhancements. • Establish and maintain integration guidelines, standards, and best practices. Drive continuous improvement initiatives for integration processes and quality metrics

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.