Senior Design for Test (DFT) Verification Engineer

Senior DFT Verification Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

Join NVIDIA, where we push the boundaries of what's possible! As a Senior DFT Verification Engineer, you will be part of a team that is at the forefront of innovation in AI and accelerated computing. This role offers you the chance to contribute to groundbreaking projects while collaborating with some highly skilled professionals in the industry. Based in Bangalore, Karnataka, you will play a crucial role in ensuring the flawless execution of our dynamic projects. If you're ambitious and passionate about making an impact, this is the perfect opportunity for you!

What you'll be doing:

• As a valued member of our team, you will take end-to-end ownership of DFX verification, pattern development, and silicon bring-up for a range of test features—including JTAG, boundary scan, security mechanisms, reliability tests like HTOL/IDDQ and test clocking—across various test modes, including multiple ATPG configurations in multi-die environments.

• Work closely with various DFX teams, CAD, and methodology teams to improve the flows and processes.

• In addition, you will help develop and deploy DFT methodologies for our next-generation products.

• Be a part of innovation to strive to improve the quality of DFT methods and AI deployment in the processes.

• You will also need to work with multi-functional teams to incorporate DFT features into the chip.

What we need to see:

• BSEE or MSEE from reputed institutions or equivalent experience with 3+ years of experience.

• You should be proficient in static timing analysis, ECO, ASIC/Logic Design Flow, HDL, and Digital logic design.

• Experience in RTL and Gates verification, simulation, and silicon bring-up.

• You need to be familiar with BIST architecture and JTAG/IEEE1149.1/1500/1687/1838.

• Strong DFT knowledge in Scan ATPG, compression techniques, and memory test.

• Strong analytical and problem-solving skills with good scripting knowledge (either Perl/Python).

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Experience Level

Senior Level