Senior ASIC Verification Engineer

Senior Engineer (Level 1)- Verification

Position:

Senior Engineer (Level 1)- Verification

Job Description:

• Experience: 4+ Years.
  
  Job Description:

  ·       Must have expertise in ASIC verification methodologies and ASIC design flow

  ·       Experience working of SV and UVM methodology and knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR or similar is required, must have executed at-least 2 SoC Verification projects

  ·       Experience in any of the listed topics: UVM, formal verification, mixed-signal simulations, power-aware simulations

  ·       Experience in setting up and debugging functional and/or gate-level simulations

  ·       Experience in translating functional requirements into verification plans

  ·       Experience in developing verification environment and regression setup.

  ·       Coverage analysis and closure

Location:

IN-KA-Bangalore, India (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services

Experience Level

Senior Level