Senior Physical Design and Signoff Engineer

Staff Engineer - Physical Design & Signoff (Synthesis to GDS2)

General Information

Job Title Staff Engineer - Physical Design & Signoff (Synthesis to GDS2) Job ID 15176 Country India City Bengaluru Date Posted 06-Feb-2026 Job Category Engineering Job Subcategory R&D Engineering Hire Type Employee Remote Eligible No

Descriptions & Requirements

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced and initiative-taking individual with a strong technical background in Physical design, physical verification and STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments and possess a passion for creating innovative technology. Your expertise lies in working with advanced Finfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of our cutting-edge technology products.

What You’ll Be Doing:

*Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors realized through ASIC design flow.
*Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics.
*Developing Digital BE activities includes synthesis, pre-layout STA, SDC constraints development, floor planning, bump placement, power planning, MV design techniques, VCLP, UPF understanding, placement, CTS, routing and collaborating with the different functional teams to achieve optimal design solutions.
*Post layout STA, timing & functional ECO development, timing signoff methodology at higher frequency IP designs closure.

*Physical verification, DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff.
*Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams.
*Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products.

The Impact You Will Have:

* Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products.
* Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages.
* Enhancing the reliability and differentiation of products in the market with reduced risk.
* Driving innovation in Physical design, physical verification, STA and signoff design methodologies and tools.
* Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions.
* Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies.

What You’ll Need:

* BS/B.Tech or MS/M.Tech degree in Electrical Engineering with 5+ years of relevant industry experience.
* Strong Physical design, physical verification, pre& post layout STA and EMIR/Power signoff experience, including SDC development, UPF/Mutlivoltage design development experience.

* Experience in DRC, LVS, DFM cleaning and timing closure is mandatory.
* Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/VCLP/PT/PT-PX/ICV and Redhawk 
* Sound understanding of Physical design, Physical verification and STA and signoff concepts.

*Experience in generating ECO for DRV cleaning and timing closure is mandatory.
* Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/PT/PT-PX 
* Sound understanding of Physical design, STA and signoff concepts.

*Proven track record of successful timing closure & tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm,3nm,2nm etc...)

*Good understanding of OCV, POCV, derates, crosstalk and design margins.
* Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. 

Who You Are:

* Proactive and detail-oriented with excellent problem-solving skills.
* Adept at working independently and providing physical design and signoff solutions.
* Excellent communicator and team player, capable of collaborating effectively with diverse teams.
* Innovative thinker with a passion for technology and continuous improvement.
* Committed to delivering high-q

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Experience Level

Senior Level