Senior Design for Testability Engineer

Senior Engineer (Level 1)- DFT

Position:

Senior Engineer (Level 1)- DFT

Job Description:

Principal Accountabilities * Responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing Analysis and sign off; * Drive implementation of comprehensive DFT plan by working with DFT and cross functional teams Job Complexity Job complexity may vary among jobs within this job level and will align with one of the job complexities listed below: (1) Incumbent has knowledge and experience in own discipline and may still be acquiring higher level knowledge and skills. Incumbent builds knowledge of the organization, processes and customers, solves a range of straightforward problems, and analyzes possible solutions using standard procedures. A moderate level of guidance and direction is provided. (2) Incumbent has extensive knowledge and experience in own discipline, possesses strong knowledge of the organization, processes and customers, solves a range of complex problems, and analyzes possible solutions using standard procedures. Limited guidance and direction is provided. Experience / Education Typically requires a 4 year degree and a minimum of 5 years of related experience; or an advanced degree without experience; or equivalent work experience.

Location:

IN-TG-Hyderabad, India-Gowra Palladium (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services

Experience Level

Senior Level