Senior Physical Design Engineer

Senior Physical Design Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Role and Responsibilities

• Own end-to-end physical implementation for SoC blocks and/or top-level designs, including floorplanning, placement, clock tree synthesis (CTS), routing and physical optimization, to achieve power, performance, and area (PPA) targets.
• Lead timing closure (setup/hold) across complex multi-mode, multi-corner (MMMC) scenarios, partnering closely with RTL, micro-architecture, STA, and signoff teams to drive convergence to timing-clean designs.
• Collaborate with design, integration, and system teams to ensure robust implementation of clocking and reset strategies, power intent (UPF/CPF), low-power features, and SoC integration requirements.
• Work closely with CAD, methodology, and technology teams to debug and resolve tool, flow, and process-related implementation challenges, and to enable adoption of new nodes and design methodologies.
• Perform and/or coordinate physical signoff activities, including DRC/LVS, IR drop, EM reliability, noise, and timing signoff, driving efficient closure of violations with minimal schedule impact.
• Complete and support tape-out readiness, including signoff checklists, ECO implementation, risk reviews, and final release activities, ensuring alignment with quality and schedule commitments.
• Contribute to post-silicon debug and silicon bring-up, correlating silicon behavior with physical invent, STA, and power analysis to root-cause issues and feed findings back into build flows.
• Identify flow gaps, quality risks, and scalability challenges, and improve productivity through scripting, automation, and development of best-practice methodologies.

Job Requirements

• 4–8 years of hands-on experience in physical design implementation for complex SoC or large-scale digital blocks, with demonstrated ownership from initial floorplanning through tape-out.
• Strong experience in block-level timing analysis and closure, including setup/hold closure across multi-mode, multi-corner (MMMC) scenarios, in collaboration with STA and signoff teams.
• Proven experience working on advanced process technology nodes (e.g., 5nm, 3nm, or equivalent), with awareness of node-specific physical design challenges and constraints.
• Proficiency with industry-standard place-and-route tools such as Cadence Innovus and/or Synopsys IC Compiler II, including ECO implementation and design optimization.
• Hands-on expertise in physical verification and signoff closure, including DRC, LVS, antenna, and related foundry checks, with the ability to efficiently debug and resolve violations.
• Strong understanding of power integrity and reliability analysis, including IR drop, electromigration (EM), noise, coupling, and crosstalk, along with effective mitigation strategies.
• Demonstrated ability to analyze and close IR/EM issues at the block level, working closely with power, signoff, and technology teams based on feedback and analysis results.
• Solid foundation in digital design fundamentals, including digital electronics, microprocessors, and computer architecture, enabling effective collaboration with RTL and architecture teams.
• Experience in bringing to bear automation and scripting (e.g., Tcl, Python, or equivalent) to improve physical develop efficiency, quality, and turnaround time.
• Exposure to AI-assisted tools and workflows, including timely engineering or analysis supported by AI, to improve debugging, optimization, or efficiency in physical development flows.
• Proven ability to mentor and guide less-experienced engineers, contributing to technical skill development, build reviews, and sharing effective approaches within the team.

Education

• B.Tech in Electronics, Electronics & Communication, or VLSI Engineering, or equivalent experience
• M.Tech in VLSI Design, Microelectronics, or Electronics Engineering

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

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Experience Level

Senior Level