Senior Principal Design Engineer - Chip Design and Test

Senior Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day

Location: Hyderabad

BE/BTECH/ME/METCH or Equivalent Degree

Job role

Job responsibilities

10-15years or Equivalent OR  Relavent

• Very good knowledge on SCAN/ATPG/JTAG/MBIST
• Experience with one or more chip tape out that includes chip ATE bring up.
• Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG)
• Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques.
• Experience in scan insertion techniques at block level and chip top level.
• Experience on Memory BIST generation, insertion, verification on RTL/Netlist level.
• Good knowledge and understanding in Analog PHY and Analog Macro tests.
• Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE1149.6 standards.
• Good knowledge on test mode timing constraints
• Good knowledge about running block level and chip STA flows.
• Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team.
• Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent tools)
• Experience with post-silicon bring up and debug on ATE.
• Good knowledge on Perl/Tcl scription skills
• Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization.
• High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project.
• Should have B-Tech/M-tech with 5 Years to 15 Years relevant experience.

• Additional Job Description

Additional Job Description

BE/BTECH/ME/METCH or Equivalent Degree

BE/BTECH/ME/METCH or Equivalent Degree

We’re doing work that matters. Help us solve what others can’t.

Experience Level

Senior Level