Senior RTL Design Engineer - ASIC Digital Design

Staff RTL Design Engineer

General Information

Job Title Staff RTL Design Engineer Job ID 17238 Country India City Noida Date Posted 27-Apr-2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No

Descriptions & Requirements

Job Description and Requirements

Staff ASIC Digital Design Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are the person who spots the glitch in the waveform before anyone else sees it. You have spent years in the weeds of RTL, chasing down timing issues and nailing the constraints that make or break a tapeout. You think in clock domains, not just blocks and buses, and you get a real kick out of untangling the edge cases that keep high-speed SERDES designs running smoothly. You do not need a spec to be perfect to get started—you ask questions, write scripts to automate the things that annoy you, and help your team close the loop on stubborn bugs. You know your way around Verilog, but you also reach for Python, Perl, or Tcl when you need to speed things up. Working with Spyglass or Tmax is second nature, and you are not afraid to call out a risky constraint or suggest a better way to check CDC/RDC. You care about quality, but you also care about helping the team move fast without tripping over the basics. At Synopsys, you will be part of a crew that obsesses over SERDES and high-speed digital design as much as you do—and you will see your work shipping in silicon used across the globe.

What You'll Be Doing

• Implement RTL designs in Verilog for SERDES interfaces and IP cores, shaping the foundation of high-speed connectivity products.
• Run Spyglass CDC/RDC/Lint and Tmax to catch clock/reset domain issues and ensure code quality from day one.
• Create and refine synthesis constraints, dialing in for robust, high-performance ASIC implementations.
• Work side by side with other design engineers to improve digital design flows and develop better methodologies.
• Support integration and verification of complex digital blocks within next-generation SERDES architectures.
• Write and maintain scripts in Perl, Shell, Python, or Tcl to automate design and verification, freeing up more time for real engineering.
• Keep up with new protocols and standards in high-speed digital design, making sure your skills and our products stay ahead of the curve.

The Impact You Will Have

• Push forward the development of SERDES IP that sets the standard for speed and reliability in the industry.
• Drive up quality and trust in our silicon by applying rigorous checks, catching issues early, and never letting standards slip.
• Help Synopsys stay at the top of the semiconductor world by delivering IP that customers depend on in critical applications.
• Make design flows smoother and more efficient—your improvements will save time and reduce errors for everyone.
• Provide practical solutions to tough digital design problems, becoming a go-to resource for your peers and adjacent teams.
• Enable larger, more complex ASIC designs to perform at their best, giving Synopsys customers a competitive edge.

What You'll Need

• B.E/B.Tech/M.Tech in Electronics & Communication Engineering, Electrical Engineering, or a related field.
• At least 3 years of hands-on ASIC digital design experience, especially with HDL coding in Verilog.
• Solid skills in building and debugging synthesis constraints, and a working knowledge of Static Timing Analysis (STA).
• Experience with Spyglass CDC/RDC/Lint and Tmax for code quality and domain crossing checks.
• Practical ability to script in Perl, Shell, Python, or Tcl for automating design and verification tasks.
• Familiarity with high-speed SERDES protocols and RTL implementation is a strong plus.

Who You Are

• You catch timing and CDC issues before they become silicon bugs, and you are not shy about flagging them.
• You can walk a junior engineer through a tricky constraint problem without losing patience or clarity.
• You write scripts to automate repetitive tasks so you and your team can focus on real design work.
• You ask for context when requirements are fuzzy and help drive the team toward clear, actionable solutions.
• You care about the details, but you never lose sight of the bigger picture—shipping great silicon that works.

The Team You'll Be Part Of

You’ll join a highly experienced and collaborative digital design team focused on advancing high-speed SERDES technology. The team is passionate about innovation, quality, and continuous improvement. Together, you will work on challenging projects that push the boundaries of connectivity and performance, learning from and supporting each other in a culture of mutual respect and shared success.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Experience Level

Senior Level