Senior IP Micro Architect - Silicon Design

Senior IP Micro Architect, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with ARM-based SoC architectures and AMBA bus protocols (e.g., AXI, ACE, APB) and experience with software implications of architectural choices and tradeoffs.
• Experience in High performance design, Multi power domains with clocking and with multiple SoCs with silicon success.
• Experience in microarchitecting digital IPs optimized for Power, Performance, and Area (PPA).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with ASIC design methodologies for front quality checks including Lint, Clock Domain Crossing/Reset Domain Crossing, Synthesis, DFT Automatic Test Pattern Generation/Memory BIST, Unified Power Format and Low Power Optimization/Estimation.
• Experience with chip design flow and understanding of cross domain involving Design Verification (DV)/DFT/Physical Design/Software.
• Experience in Static Timing Analysis (STA) closure, DV test-plan review and coverage analysis of the sub-system and chip level verification.
• Proficiency in Process Cores, Interconnects, Debug, Trace, Security, Interrupts, Clocks, Power Domains, and Pin-muxing.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Define the detailed microarchitecture of complex digital IPs, focusing on optimizing for Power, Performance, and Area (PPA).
• Create comprehensive microarchitecture specifications, including block diagrams, interface definitions, data flows, pipeline structures, and state machines.
• Guide and mentor RTL design teams during the implementation phase, ensuring adherence to the microarchitecture specification.
• Review RTL code for correctness, completeness, quality, and adherence to design guidelines.
• Work with the verification team to develop test plans and review coverage analysis, ensuring thorough validation of the IP.

Experience Level

Senior Level