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SoC Design Engineer Job Descriptions &amp; RequirementsThis person will be part of the next generation Design team. Requires strong hands-on knowledge of all facets of the SOC design process and good understanding of SOC Architecture. Key Responsibilities:• Strong knowledge in IP/SOC design methodologies.•Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog• Strong experience in Synthesis, timing, full chip netlist &amp; front-end design tools&amp; flows Low power design• Mentoring juniors and enhancing their skill set• Must have strong knowledge of AMBA AHB/AXI protocol• Working knowledge on code coverage, functional coverage, Lint, CDC etc• IP development and coding using standard coding guide lines knowledge• Excellent communication skills. Must be able to participate &amp; lead in global meetings• Soft skills to be able to work in a cross functional international team digital and software design engineers Preferred Experience:• 4-10 years of RTL design, ArchitectureSOC implementation experience:• Ability to work well in a dynamic, fast-paced, pressure filled environment.

Modernize Chip Solutions

Embedded Systems Engineer

PD Engineer Experience:&nbsp;3-8 YearsPosition Requirements• Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.• Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.• Successful track records of taping out complex, 16nm/10nm/7nm/5nm/3nm SOC chips.• Automation and programming-minded, solid coding experience in Tcl/Perl/Python.• Innovative, self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.• Strong timing analysis skills.• Strong physical implementation flow debugging skills.• Strong scripting skills.

Junior Mechanical Engineer

Senior SERDES Design Engineer<h4>
 
 General Information
 </h4>






 Job Title
 

 Senior SERDES Design Engineer
 



 Job ID
 

 12391
 



 Country
 

 India
 



 City
 

 Hyderabad
 



 Date Posted
 

 28-Jul-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 Analog Design
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

<h4 id="isPasted">We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.<h4>You Are:</h4>You are a highly motivated, detail-oriented, and technically adept engineer with a passion for analog and mixed-signal IC design. With a strong foundation in CMOS technology and a keen interest in high-speed circuit architectures, you thrive in fast-paced, collaborative environments where innovation and precision are paramount. You are curious, proactive, and always eager to explore the latest advancements in semiconductor design, particularly within the SERDES domain. Your approach to problem-solving is both analytical and creative, allowing you to devise robust solutions to complex challenges.What You’ll Be Doing:<ul><li>Designing, developing, troubleshooting, and debugging multi-Gb/s SERDES IP for a variety of high-performance applications.</li><li>Translating SerDes standards and block specifications into innovative circuit architectures and effective design strategies.</li><li>Collaborating closely with a cross-functional team of analog and digital designers from diverse backgrounds to deliver integrated solutions.</li><li>Utilizing a comprehensive suite of IC design tools, enhanced by proprietary in-house tools, to optimize design workflows and outcomes.</li><li>Ensuring all designs adhere to stringent performance, reliability, and manufacturability requirements through rigorous analysis and validation.</li><li>Documenting design methodologies, processes, and results to foster knowledge sharing and support future engineering initiatives.</li></ul><h4> </h4><h4>The Impact You Will Have:</h4><ul><li>Contributing to the development of cutting-edge, high-speed analog integrated circuits that power the world’s most advanced technologies.</li><li>Enhancing the performance, reliability, and scalability of SERDES IP deployed in a wide range of industries and applications.</li><li>Driving innovation in analog and mixed-signal design, setting new standards for quality and efficiency.</li><li>Collaborating with a talented team to deliver world-class design solutions that support Synopsys’ leadership in the semiconductor industry.</li><li>Supporting Synopsys' analog and mixed-signal R&amp;D initiatives, helping to shape the direction of future product development.</li><li>Ensuring seamless integration of analog and digital components in complex system-on-chip (SoC) environments.</li></ul><h4> </h4><h4>What You’ll Need:</h4><ul><li>2-4 yrs relevant experience with BTech / MTech </li><li>In-depth familiarity with transistor-level circuit design and CMOS design fundamentals.</li><li>Hands-on exposure to SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, ADC, BGR, regulators).</li><li>Awareness of ESD (electrostatic discharge) issues and circuit techniques for effective mitigation.</li><li>Experience with custom digital design tailored for high-speed logic paths.</li><li>Solid understanding of design for reliability (e.g., EM, IR, aging) and layout effects (e.g., matching, proximity effects).</li><li>Proficiency in industry-standard custom design tools such as Cadence, HSPICE, PRIMESIM, and Ultrasim.</li><li>Experience with scripting languages for simulation post-processing (e.g., TCL, PERL, MATLAB).</li><li>Familiarity with system-level budgeting for jitter, amplitude, noise, etc.</li><li>Awareness of signal integrity issues, including packaging effects, board parasitics, crosstalk, and noise.</li></ul><h4> </h4><h4>Who You Are:</h4><ul><li>Collaborative, open-minded, and respectful of diverse perspectives.</li><li>Excellent communicator with the ability to convey complex technical concepts clearly.</li><li>Self-driven, proactive, and comfortable working independently as well as in a team setting.</li><li>Analytical thinker with strong problem-solving abilities and attention to detail.</li><li>Adaptable to changing priorities and able to thrive in a dynamic, innovation-driven environment.</li><li>Committed to continuous learning and professional growth.</li></ul><h4> </h4><h4>The Team You’ll Be A Part Of:</h4>You will be joining a world-class team of analog and mixed-signal design experts dedicated to developing high-performance SERDES IP. The team values innovation, collaboration, and a culture of knowledge sharing. You’ll work alongside passionate engineers and leverage the support of experienced software and CAD professionals, all united by a shared commitment to excellence and technological advancement.<h4>Rewards and Benefits:</h4>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</h4>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Synopsys India Pvt Ltd

Senior Design Engineer

Senior Staff Analog Design Engineer<h4>
 
 General Information
 </h4>






 Job Title
 

 Senior Staff Analog Design Engineer
 



 Job ID
 

 10827
 



 Country
 

 India
 



 City
 

 Hyderabad
 



 Date Posted
 

 21-Apr-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 Analog Design
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

<h4 id="isPasted">We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.<h4>You Are:</h4>You are a passionate and highly skilled engineer committed to advancing the field of high-speed analog design. You bring a wealth of experience in designing critical analog and mixed-signal blocks, particularly for cutting-edge PCIe 6 and PCIe 7 or SerDes PHY solutions. Your technical expertise encompasses transistor-level design, deep knowledge of CMOS (including finFET and SOI processes), and a proven ability to create robust high-speed building blocks—such as LDOs, Bandgap references, ADC/DACs, PLLs, and DLLs—that consistently meet rigorous performance, power, and area targets.You thrive in collaborative, multidisciplinary environments, where your clear communication and mentoring skills empower both peers and junior engineers to excel. Your proactive approach to problem-solving and your dedication to continuous improvement ensure that you stay at the forefront of technology trends. You are adept at analyzing and mitigating jitter, maintaining signal integrity, and ensuring compliance with demanding industry standards. Your experience with porting PHY designs across technology nodes demonstrates your adaptability and commitment to delivering high-quality, innovative solutions. You value documentation, knowledge sharing, and actively contribute to a culture of learning and technical excellence.Most importantly, you are excited to join a team that values diversity, encourages bold ideas, and is committed to shaping the future of high-speed connectivity. You see challenges as opportunities and bring a growth mindset to every project you undertake.<h4>What You’ll Be Doing:</h4><ul><li>Designing and developing advanced analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY architectures under the guidance of senior technical leaders.</li><li>Ensuring that all designs strictly adhere to PCIe protocol standards, optimizing for performance, power, and area efficiency.</li><li>Porting high-speed PHY designs to various technology nodes while maintaining signal integrity and maximizing performance.</li><li>Collaborating with cross-functional teams—including digital, verification, and layout groups—to successfully integrate analog circuits into complex SerDes PHY systems.</li><li>Implementing innovative verification strategies for high-speed analog/mixed-signal circuits using state-of-the-art simulation and modeling tools.</li><li>Working closely with layout teams to minimize parasitics, device stress, and process variation impacts on overall circuit performance.</li><li>Analyzing simulation and silicon measurement data to validate designs and ensure compliance with PCIe standards.</li><li>Mentoring junior engineers and promoting best practices in analog/mixed-signal design and verification.</li><li>Documenting design features, specifications, and test methodologies for future reference and team knowledge sharing.</li><li>Partnering with characterization teams to validate electrical performance of circuits in silicon and resolve technical challenges.</li></ul><h4>The Impact You Will Have:</h4><ul><li>Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, advancing high-speed interface technologies that power tomorrow’s data-driven world.</li><li>Ensure Synopsys’ analog/mixed-signal circuits exceed industry standards, reinforcing our reputation for technical excellence and innovation.</li><li>Facilitate seamless integration of analog circuits into sophisticated SerDes PHY systems, enhancing overall performance and reliability.</li><li>Mentor and develop junior engineers, fostering a collaborative and innovative team environment.</li><li>Lead successful porting of PHY designs across multiple technology nodes, delivering versatile and scalable solutions for diverse customer needs.</li><li>Strengthen verification and validation processes, resulting in robust, reliable, and high-performing analog/mixed-signal circuits.</li></ul><h4>What You’ll Need:</h4><ul><li>PhD with 3+ years, or MTech/MS with 7+ years of experience in analog/mixed-signal circuit design focused on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs.</li><li>Proven expertise in transistor-level design of high-speed analog building blocks (e.g., LDOs, Bandgap references, ADC/DACs, PLLs, DLLs).</li><li>Demonstrated silicon experience in developing PHY circuits compliant with PCIe standards.</li><li>Strong background in high-speed SerDes AFE development, including CTLE and CDR design.</li><li>Experience designing high-speed SerDes transmitters and deep knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis).</li><li>Solid foundation in jitter budgeting analysis and expertise in minimizing jitter impact on signal integrity.</li><li>Experience porting PHY designs across different technology nodes and deep knowledge of CMOS, finFET, and gate-all-around processes.</li><li>Comprehensive understanding of the PCIe protocol, signal integrity, jitter performance, and high-speed clocking.</li><li>Ability to collaborate with layout teams to minimize parasitics, process variations, and electromigration effects.</li><li>Proven track record of effective teamwork and successful project outcomes across multidisciplinary teams.</li></ul><h4> </h4><h4>Who You Are:</h4><ul><li>Innovative thinker with a passion for high-speed analog design and technology advancement.</li><li>Collaborative team player who values diversity and inclusion.</li><li>Effective communicator, able to translate complex technical concepts to a variety of audiences.</li><li>Mentor and coach, eager to support the development of junior engineers.</li><li>Detail-oriented problem solver with a commitment to quality and continuous improvement.</li><li>Adaptable and resourceful, thriving in fast-paced, changing environments.</li></ul><h4>The Team You’ll Be A Part Of:</h4>You will join a world-class analog/mixed-signal design team at Synopsys, focused on developing high-speed interface IP for next-generation semiconductor products. The team is composed of passionate engineers from diverse backgrounds, collaborating closely to deliver innovative solutions that drive the future of connectivity. Our culture emphasizes technical excellence, knowledge sharing, and continuous learning, providing an environment where your skills and ideas are valued and your career can thrive.<h4>Rewards and Benefits:</h4>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</h4>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Electronic Engineer

Senior Staff Applications Engineer<h4>
 
 General Information
 </h4>






 Job Title
 

 Senior Staff Applications Engineer
 



 Job ID
 

 12246
 



 Country
 

 India
 



 City
 

 Bengaluru
 



 Date Posted
 

 17-Jul-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 Applications Engineering
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

<h4 id="isPasted">Alternate Job Titles:</h4><ul><li>Senior Staff Applications Engineer</li><li>Post-Sales Application Engineer – Interface IP</li><li>Technical Solutions Engineer – IP Integration</li><li>Staff Engineer – Customer Success (IP)</li></ul><h4>We Are:</h4>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.<h4>You Are:</h4>You are a deeply skilled engineering professional with a passion for enabling the success of others. You thrive in a dynamic, customer-facing environment, where your technical expertise and problem-solving abilities are tested daily. You have a strong foundation in ASIC/SoC front-end design, with hands-on experience in RTL coding, synthesis, timing analysis, and formal verification. You’re adept at debugging complex designs—whether in simulation, emulation, or actual silicon—and you understand the intricacies of at least one industry-standard protocol such as USB. Collaboration is at the heart of your work style: you communicate effectively with both customers and internal teams, translating technical needs into actionable solutions. You take initiative, anticipate challenges, and enjoy the satisfaction of resolving tough issues. Your high degree of self-motivation, personal responsibility, and analytical rigor ensures that you deliver results even under pressure. You are eager to share best practices, drive continuous improvement, and contribute to the broader success of your team and customers alike. If you are excited about tackling new challenges, committed to excellence, and ready to make a real impact in the semiconductor industry, you will find your place at Synopsys.<h4>What You’ll Be Doing:</h4><ul><li>Providing expert technical support to customers integrating Synopsys Interface IPs into their SoC designs.</li><li>Analyzing and resolving complex issues related to IP configuration, integration, and usage across various platforms.</li><li>Interfacing directly with customers to understand their design and verification flows, identifying both current and future needs.</li><li>Collaborating with cross-functional teams to address and resolve customer challenges efficiently.</li><li>Debugging and troubleshooting designs in simulation, emulation, and silicon environments.</li><li>Driving the adoption of best practices and lessons learned from customer interactions back into product development.</li><li>Proactively engaging with customers during integration and silicon debug phases to ensure successful deployment.</li></ul><h4>The Impact You Will Have:</h4><ul><li>Accelerating customer time-to-market by providing timely and accurate technical guidance.</li><li>Enhancing customer satisfaction and trust in Synopsys’ IP solutions through effective support and problem resolution.</li><li>Contributing real-world feedback to product development, improving the robustness and usability of Synopsys IP.</li><li>Reducing post-sales escalations and ensuring smooth IP integration for major industry players.</li><li>Fostering long-term customer partnerships by consistently exceeding expectations.  </li><li>Helping shape the direction of next-generation IP products based on customer needs and industry trends.</li></ul><h4>What You’ll Need:</h4><ul><li>Bachelor’s or Master’s Degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.</li><li>Minimum 8 years of relevant experience in ASIC/SoC front-end design, including RTL coding (Verilog), logic and clock tree synthesis, static timing analysis, and equivalence checking.</li><li>Full understanding of digital design methodologies and tools, including formal verification.</li><li>Domain knowledge of at least one interface protocol (e.g., USB); experience with additional protocols (PCIe, DDR, SATA, HDMI, MIPI, Ethernet) is a plus.</li><li>Experience supporting at least one ASIC/SoC tape-out from concept to full production.</li><li>Strong silicon debug and troubleshooting skills are highly desirable.</li></ul><h4>Who You Are:</h4><ul><li>Technically creative, results-oriented, and able to manage multiple priorities efficiently.</li><li>Strong communicator who can explain complex technical concepts to diverse audiences.</li><li>High degree of self-motivation and personal responsibility.</li><li>Excellent analytical, reasoning, and problem-solving skills with keen attention to detail.</li><li>Collaborative team member who thrives in cross-functional environments.</li></ul><h4>The Team You’ll Be A Part Of:</h4>You will join the Solutions Group at Synopsys, a highly collaborative team dedicated to delivering world-class IP solutions and customer success. Working closely with experts in design, verification, applications engineering, and product development, you will be at the forefront of supporting and enabling the most innovative semiconductor companies across the globe. Our team values knowledge sharing, continuous learning, and a proactive approach to solving the industry’s toughest challenges.<h4>Rewards and Benefits:</h4>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Senior Application Engineer

BSP Developer Key Skills:&nbsp;◾ BSP (Board Support Package) Development&nbsp;◾ Embedded Systems Programming&nbsp;◾ Diag, USB, Storage, PMIC&nbsp;◾ Expertise in Clock Management, Buses &amp; Peripherals&nbsp;◾ Strong Knowledge of Memory Management in Embedded Systems Experience: 3 – 5 Years Share your updated resume now.

MosChip Technology Ltd

Developer

Linux Device Driver Developer Capgemini is hiring for Linux Device Driver Developer (LDD) can join in 30 Days, and possess the required skill set, apply to this job. Experience: 4- 10 years Key Requirements:1. 3-5 Yrs of experience in Embedded Linux Kernel/Drivers domain2. Embedded Software development and porting on Linux and ARM platforms3. Strong Programming skills on C &amp; Data Structures4. Expertise on OS (Memory Mgmt, Scheduling, IPC, Multi-threading/processing)5. Experience in Linux Kernel/Device Drivers6. Proficiency in debugging embedded systems, including using tools like JTAG7. Understanding of System architecture and debugging at a system level. Please send your resume with the following details:Subject Line: Job Application- LDD (Linux Device Drivers)Name:Total Exp:Rel exp:Current CTC:ECTC:Current location:Are you willing to relocate?Notice period/ LWD:

Capgemini

Linux Engineer

Embedded Software Developer- Automotive Experience:&nbsp;4-8 YearsJob Category:&nbsp;Embedded Software You will be responsible for :• Implement sensing, control algorithms• Device drivers development for embedded controllers•Develop automotive software components according to AUTOSAR Model-Based Design• Deliver highly reliable system-level software• Follows safety and regulatory compliance requirements. Skills:• Strong C Experience• Understanding of MISRA-C guidelines• Experience with ADAS, Infotainment, V2X, Telematics features• Experience with QNX, LYNXOS-178 or Automotive Grade Linux• Experience with CAN, CAN-FD, SAE J1939, UDS/ISO 14229, LIN• Comprehensive experience with Vector CAN Tools (CANalyzer, CANoe)• Experience with OCPP, ISO 15118, OBD2 (SAE J1979), AUTOSAR standards• Strong analytical and debugging skills

Embedded Software Developer

Emulation Engineer We are excited to announce an amazing opportunity to work with Emulation Engineer.Experience: 6 TO 12 years Responsibilities• Develop RTL models for IPs, subsystems, and SoCs using Verilog/SystemVerilog• Build emulation models from scratch and integrate Transactors/AVIPs• Work with emulation platforms (Cadence Palladium, ZeBu, Mentor Veloce) for model compilation, test execution, and debugging• Write and port sanity testcases (SCEMI/DPI) for emulation compatibility• Configure and manage emulation environments, servers, and clusters• Execute emulation-specific verification plans and debug runtime flows• Strong protocol knowledge: ARM cores, PCIe Gen4/5, JTAG, SPI, UART, I2C, USB2/3, HDMI, DisplayPort, Ethernet (1G–10G) Automation &amp; Scripting:• Proficient in Unix shell scripting, Python, Perl, Tcl• Automate emulation tasks, regression flows, and CI pipelines If you're a tech-savvy professional looking to make an impact, we’d love to hear from you!

Capgemini Engineering

Infrastructure Engineering IIIYour role will be instrumental in shaping the future at one of the world's largest and most influential companies.As a member of our Infrastructure Platforms Engineering team, you will  join a high-performing team dedicated to developing and deploying large-scale infrastructure solutions that support JPMorgan Chase and Co.’s diverse and critical businesses. You'll be using the latest technologies, data management, and security practices in all aspects of Infrastructure and software development. Critical thinking, clear communication, and collaboration are key to successful product delivery. Job responsibilities<ul><li>Executes creative solutions for the design, development, and technical troubleshooting for problems of high complexity</li><li>Applies technical expertise and problem-solving methodologies to projects of large scope</li><li>Drives a work stream or project consisting of one or more infrastructure engineering technologies</li><li>Works with other platforms to architect and implement changes required to resolve issues and modernize the organization and its technology processes</li><li>Strongly considers upstream/downstream data and systems or technical implications and advises on mitigation actions</li><li>Adds to team culture of diversity, equity, inclusion, and respect</li><li>Flexible to work in off hours/weekends &amp; in 24x7 on-call rotation.</li></ul> Required qualifications, capabilities, and skills<ul><li>Formal training or certification on infrastructure engineering concepts and 3+ years applied experience</li><li>Very good understanding in multiple infrastructure technologies and protocols including Global and Local load balancing, DNS, network routing, switching, firewalls and proxies.</li><li>Good knowledge and understanding of REST/JSON, API implementation and container based technologies.</li><li>Experience with programmatic methods of network device interaction, configuration and lifecycle management.</li><li>Thorough understanding of business technology drivers and their impact on architecture design, performance and monitoring, best practices.</li><li>Strong critical-thinking and problem-solving skills with clear communication.</li><li>Ability to collaborate with different teams and roles to achieve common goals.</li><li>Hands on experience with Atlassian products such as JIRA, Bitbucket, and Confluence.</li><li>Advanced knowledge and experience with network load balancing in F5 Load balancing technology (GTM, LTM, ASM, APM, AFM)</li><li>Extensive experience working in operations and troubleshooting complex configuration or device issues in Load balancing.</li><li>Experience working in CLI (command line interface) </li></ul> Preferred qualifications, capabilities, and skills<ul><li>F5 Certifications will be preferred but not desirable, like BIG-IP TMOS Administration (201) and LTM Technology Specialist (301)</li><li>Proficient in one programming language (ex. Python) and automation framework (Ansible)</li><li>Ability to multi-task across project/initiatives and deliver according to time commitments</li><li>Experience with Infrastructure as Code – IaC implementation. </li></ul><h4>Experience Level</h4>Senior Level

JP Morgan Services India Pvt Ltd

Technical Engineer

Principal - ASIC Digital Design (Physical Implementation/Design/STA)<h4>
 
 General Information
 </h4>






 Job Title
 

 Principal - ASIC Digital Design (Physical Implementation/Design/STA)
 



 Job ID
 

 6673
 



 Country
 

 India
 



 City
 

 Noida
 



 Date Posted
 

 28-Sep-2024
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 ASIC Digital Design
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

Principal - ASIC Digital Design (Physical Implementation/Design/STA, experience - 12+ Years) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What You’ll Be Doing: * Working on new processes for physical implementation flows and cutting-edge technology nodes. * Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. * Defining signoff criteria with a strong focus on Timing Closure. * Maturing the physical implementation guide used for customers and internal hardening teams. * Participating in next-generation physical design methodology and flow development. * Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. * Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints. The Impact You Will Have: * Ensuring the optimization and successful implementation of cutting-edge technology nodes. * Contributing to the development of high-performance silicon chips and software content. * Enhancing the efficiency and performance of Synopsys’ IPs through rigorous timing closure and signoff criteria. * Improving customer satisfaction by maturing physical implementation guides. * Supporting the achievement of Synopsys' operational goals through innovative design solutions. What You’ll Need: * Extensive experience with ASIC design flow and hierarchical physical design strategies. * Strong background in timing analysis, constraints management, and frontend synthesis. * Experience with physical-aware synthesis, formality, and various verification strategies. * Knowledge of Primepower-based power analysis and clock gating for power reduction. * Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. * Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team You’ll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Mechanical CAD Designer

Teamcenter/PLM ArchitectWe are seeking a highly skilled Senior Software Engineer with a strong background in Product Lifecycle Management (PLM) systems and cloud-based solutions. The ideal candidate will have extensive experience with Java/Spring Boot, microservices architecture, and cloud platforms, particularly Google Cloud Platform (GCP). Proficiency in NOSQLDB is also required.Strong knowledge in PLM Teamcenter Architecture, Customization (ITK, SOA, RAC and AWC) and configurations. Design and build scalable microservices using Java/Spring Boot.Leverage Google Cloud Platform (GCP) to deploy, manage, and optimize cloud-based applications.Utilize MongoDB for data storage, ensuring optimal performance and reliability.Collaborate with cross-functional teams to integrate PLM systems with other enterprise applications.Participate in the full software development lifecycle, including requirements gathering, design, development, testing, and deployment.Troubleshoot and resolve technical issues, providing timely and effective solutions.Strong knowledge in PLM Teamcenter Architecture, Customization (ITK, SOA, RAC and AWC) and configurations. Design and build scalable microservices using Java/Spring Boot.Leverage Google Cloud Platform (GCP) to deploy, manage, and optimize cloud-based applications.Utilize MongoDB for data storage, ensuring optimal performance and reliability.Collaborate with cross-functional teams to integrate PLM systems with other enterprise applications.Participate in the full software development lifecycle, including requirements gathering, design, development, testing, and deployment.Troubleshoot and resolve technical issues, providing timely and effective solutions.<h4>Experience Level</h4>Senior Level

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