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Full Stack Architect <ul><li>Lead innovation with Vue.js, Node.js, Python, and cloud-native tools like Docker, Kubernetes, Helm, and Kafka. </li><li>Build high-performance, scalable applications, design APIs, and manage multi-environment deployments.</li><li>Short joiners preferred</li></ul> Share your updated resume now.

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Analog Layout Engineer We are hiring for below skills.Role: Analog Layout EngineerRequirement: looking for TSMC Lower nodes &lt;10nm.Experience: 6+ yearsLocation: Bangalore If Interested, please share resume.

Capgemini

Electronic Engineer

STA Engineer We are hiring for below skills.Role: STA EngineerExperience: 4+ yearsLocation: Bangalore If Interested, please share resume.

Associate Engineer

GLS engineer We are looking for GLS engineer with 5+yrs of experience for Bangalore location. Brief JD:<ul><li>Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years</li><li>hands on experience in GLS (Zero Delay, SDF, PAGLS)</li><li>Excellent debugging skills and fixing issues</li><li>Knowledge in SV/UVM and test bench flow</li><li>Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.</li><li>Understanding of SOC Architecture</li></ul> If interested, please share your profile.

Capgemini Engineering

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Memory /Custom Layout Design Professional We are hiring for \"Memory /Custom Layout Design\". Requirement<ul><li>Sound knowledge &amp; hands on experience in Finfet technology, layout design and DRC limitations.</li><li>Proficient in physical verification flow &amp; debug, like DRC, LVS, ERC, Boundary conditions.</li></ul> Location: BangaloreExperience: 3 to 9years. If interested, you can share resume.

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Emulation Engineer We are hiring for below skills.Role: Emulation Engineer with ZebuExperience: 5+ yearsLocation: Bangalore If Interested, please share resume.

Embedded Systems Engineer

ASIC RTL Design Lead We are hiring for below - Role: ASIC RTL Design LeadExperience: 7+ yearsLocation: Bangalore If interested, you can share profile.

Design Verification Lead We are hiring for below - Role: Design Verification LeadExperience: 7+ yearsLocation: Bangalore If interested, you can share profile.

Assistant Design Engineer

PRINCIPAL SW SYSTEMS ENGINEER 9592- Routing Protocol DevelopmentRoles &amp; Responsibilities: Experience: 15+ Years • Exposure to the entire Product Life Cycle • Micro services-based Architecture, working experience with Docker containers, Kubernetes (K8s, K3s) cluster, Helm charts • Strong coding and debugging experience using Golang or C • Linux OS, Data structures, IPC mechanisms. Understanding of multi-threading/routines. • Agile Development Model with CI/CD, Jenkins pipeline and working knowledge of Git environment. • Working knowledge of OpenConfig NETCONF/GNMI/GRPC • Proficiency in L2/L3 OSI layer Protocols - LACP ; LAGs; BGP ; BFD; EVPN; MPLS/VPLS; ARP; and L2 switching; L3 Routing • Good Written/Verbal Communication Skills<h4>Experience Level</h4>Senior Level

Extreme Networks India Private Limited

Assistant software Engineer

Member Of Technical Staff - HW QualWe’re in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry.This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.If you, like us, say “bring it on” to exciting challenges that change the world, we have endless opportunities where you can make your mark.The FlashArray team builds the industry’s most innovative, high-performance, and highly available portfolio of products that are designed for the most demanding mission critical applications.  While we deliver a hardware storage array, over 90% of our engineering staff are software engineers. Our customers are the most important part of our business and they love FlashArray for it's simplicity of management, the constant flow of new and exciting upgrades, and ability to live on the cutting edge of technology while never taking downtime, ever. Most recently, we extended the value of our FlashArray capabilities into the cloud with CloudSnap and Cloud Block Store for AWS. These new innovations enable our customers to leverage the agility of the public cloud for both traditional IT and cloud-native applications.  What you'll be doing:<ul><li>Ensuring FlashArray and FlashBlade products and features ship with the highest quality.</li><li>Create System test designs that focus on FlashArray and FlashBlade</li><li>Enable software testbeds to run tests which validate HW quality</li><li>Find statistical and systemic hardware issues earlier in programs</li><li>Work with Support and Escalation teams to help reproduce and root cause customer issues Identifying, analyzing, and documenting any defects discovered during testing.</li><li>Design and build tools that make it efficient to execute and triage a large number of test scripts.</li><li>Understand the inner workings of features to target specific failure domains in our stack to make the product/features fault tolerant and resilient.</li><li>Continuously look for test gaps, perform root cause analysis &amp; close loop on customer found defects.</li></ul>WHAT YOU’LL NEED TO BRING TO THIS ROLE...<ul><li>BS in Computer Science or equivalent.</li><li>8+ years of software system testing experience, or equivalent.</li><li>6+ years of hands-on automation in Python or similar scripting languages.</li><li>Strong knowledge of System testing using end-to-end Automation</li><li>Familiarity with running Jenkins environment</li><li>Familiarity with X86 hardware designs, as well as aspects like BMC BIOS, networking and other system software aspects</li><li>Experience in developing test strategies for server hardware validation </li><li>Good to have some exposure to enterprise products in cloud and container platforms (AWS, Azure, Google Cloud, Kubernetes, Docker).</li><li>Experience with any  virtualization technologies: VMware, Hyper-V, OpenStack, Oracle deployment and customer use cases.</li><li>Experience with multiple operating systems: Linux, Windows.</li><li>Preferred but not required - storage protocols Fibre Channel, FCoE, iSCSI, NVME.</li><li>Ability to independently deploy and maintain test environments.</li><li>Proven analytical and creative problem-solving abilities.</li><li>Capable of prioritizing multiple projects in a fast-paced environment.</li><li>Natural curiosity with excellent written, oral, and interpersonal communication skills.</li><li>Must be willing and able to work in an open office, team environment.</li></ul>WHAT YOU CAN EXPECT FROM US:<ul><li>Pure Innovation: We celebrate those who think critically, like a challenge and aspire to be trailblazers.</li><li>Pure Growth: We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area™, Fortune's Best Workplaces for Millennials™ and certified as a Great Place to Work®!</li><li>Pure Team: We build each other up and set aside ego for the greater good.</li></ul>And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out <a href="http://purebenefits.com">purebenefits.com</a> for more information.ACCOMMODATIONS AND ACCESSIBILITY:Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at <a href="mailto:TA-Ops@purestorage.com">TA-Ops@purestorage.com</a> if you’re invited to an interview.OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM:We’re forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn’t just accepted but embraced. That’s why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership. Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.<h4>Experience Level</h4>Senior Level

Pure Storage India Pvt Ltd

Member Of Technical Staff

Principle/ Sr Staff - Physical Design & PnR<h4>
 
 General Information
 </h4>






 Job Title
 

 Principle/ Sr Staff - Physical Design &amp; PnR
 



 Job ID
 

 8878
 



 Country
 

 India
 



 City
 

 Bengaluru
 



 Date Posted
 

 21-Jan-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 R&amp;D Engineering
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.<h4>You Are:</h4>You are a passionate and dedicated R&amp;D Staff Engineer with a deep understanding of physical design and a knack for solving complex design challenges. With a strong background in place &amp; route, timing closure, and power optimization, you thrive in dynamic environments where technological advancements are constant. Your expertise in low-power, high-performance design, especially with advanced nodes under 5nm, sets you apart. You are familiar with industry-leading tools like Fusion Compiler, Primetime, and Formality, and you bring a solid knowledge of scripting languages such as TCL, Perl, and Python. You hold a BS or MS in Electrical Engineering or a related field, with over 5 years of relevant experience. Your strong investigative and problem-solving skills, combined with your enthusiasm for learning new technologies, make you a perfect fit for our innovative team. Excellent communication skills in English, self-motivation, and a result-oriented mindset are essential traits you possess.<h4>What You’ll Be Doing:</h4><ul><li>Developing and implementing innovative methodologies for high-performance cores and IPs.</li><li>Collaborating with a global team to enhance PPA (Performance, Power, Area) metrics.</li><li>Utilizing advanced technologies and tools to improve design quality and process efficiency.</li><li>Contributing to both flow development and the implementation of complex IPs.</li><li>Addressing top-notch critical design challenges using Synopsys implementation tools.</li><li>Staying updated with the latest technology nodes and industry trends.</li></ul><h4>The Impact You Will Have:</h4><ul><li>Driving innovation in high-performance core and IP implementation methodologies.</li><li>Enhancing the efficiency and predictability of the implementation process.</li><li>Improving the quality of results through advanced technological applications.</li><li>Contributing to the development of cutting-edge semiconductor technologies.</li><li>Solving complex design challenges to achieve best-in-class PPA and TAT targets.</li><li>Supporting the continuous advancement of Synopsys' technological capabilities.</li></ul><h4>What You’ll Need:</h4><ul><li>Deep knowledge of physical design, place &amp; route, timing closure, and power optimization.</li><li>Experience in low-power, high-performance design and advanced nodes under 5nm.</li><li>Familiarity with Fusion Compiler, Primetime, and Formality.</li><li>Proficiency in scripting languages such as TCL, Perl, and Python.</li><li>A BS or MS in Electrical Engineering or a related field with 5+ years of relevant experience.</li></ul><h4>Who You Are:</h4><ul><li>Self-motivated, enthusiastic, and result-oriented.</li><li>Strong investigative and problem-solving skills.</li><li>Eager to learn and explore new technologies.</li><li>Excellent communication skills in English.</li><li>Knowledge of high-performance CPUs/GPUs and interface IP controllers like UCie, PCIe, USB is a plus.</li></ul><h4>The Team You’ll Be A Part Of:</h4>You will join a growing global team at Synopsys focused on advancing state-of-the-art high-performance cores/IPs implementation. This team is responsible for developing innovative methodologies to implement CPUs/GPUs and interface IPs that deliver more performance with less power. You will work with industry-leading Synopsys implementation tools and tackle the most complex design challenges, contributing to the continuous improvement of PPA metrics and the achievement of best-in-class targets.<h4>Rewards and Benefits:</h4>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Synopsys India Pvt Ltd

Junior Designer

Technologist, ASIC Development Engineering (Physical Design)<h4>Company Description</h4>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.<h4>Job Description</h4>Position Overview:We are looking for a highly skilled and experienced individual for SoC PD lead position for driving SoC implementation efforts from RTL to GDSII. This role is pivotal within our talented team of engineers, ensuring that we meet our GDS release timelines, PPA requirements, and all sign-off criteria for our complex semiconductor designs. This role demands a profound technical understanding of the entire implementation cycle, from start to finish, as well as exceptional leadership skills. The successful candidate will work with various functional teams and must possess a strategic vision to drive continuous improvement in our methodologies and processes. Key Responsibilities:<ul><li>To be responsible for leading RTL-to-GDSII SoC implementation effort</li><li>To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc.</li><li>To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity.</li><li>To ensure process compliance during project execution and enable / participate in technical discussions/reviews.</li><li>To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.</li><li>Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow</li><li>Foster a culture of innovation, collaboration, and continuous improvement</li></ul>-<h4>Qualifications</h4>- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field- A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs <ul><li>Proven ability in technically leading a small/medium-sized team for executing projects preferred.</li><li>Hands-on experience on the entire PD Flow from RTL to GDSII</li><li>Should have a good understanding of Floor planning, Power Planning, Placement &amp; Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains.</li><li>Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)</li><li>Exposure to static timing analysis fixes including automated ECO generation.</li><li>Strong in areas on CTS, Power, Bump planning, Floorplan</li><li>Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies.</li><li>Library preparation in any environment (Synopsys, Cadence, etc)</li><li>Working knowledge on Physical verification tasks at lower nodes (database merging/DRC/LVS/ERC/PERC/Antenna/ESD/LUP analysis/fixing) at block level/chip level</li><li>The job would require complete ownership from RTL to GDS for complete SoC</li><li>Exposure to IP Hardening for blocks like SERDES, USB PHY, PCIe, DDR will be an added advantage.</li><li>Working knowledge of scripting languages like Perl and TCL will be considered a plus</li><li>Candidate needs to be self-driven and confident in reporting the status and sharing technical results with customers.</li><li>Must have the ability to present to senior management, work in a geographically dispersed team, and be aware of cross-cultural nuances.</li><li>Should be able to define project milestones, identify risks, and call out mitigation plans.</li></ul> <h4>Additional Information</h4>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying<h4>Experience Level</h4>Senior Level

SanDisk India Device Design Centre Pvt.Ltd

Principal Engineer, ASIC Development Engineering (IP Verification)<h4>Company Description</h4>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.<h4>Job Description</h4>We are seeking a highly skilled and experienced Principal Engineer to join our ASIC Development Engineering team in Bengaluru, India.In this role you will  design and implements IPs and subsystems.Dealing the best of class IPs for all SanDisk products<ul><li>BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field</li><li>8+ years of experience in ASIC development, with a proven track record of leading complex project</li><li>At  hands on in IP / blocks / subsystem complex design in verilog / sysverilog</li><li>Strong digital design development and execution skills , solving bugs</li><li>Experience in grooming team of 1-4 engineers, interacting with many team</li><li>Deep expirience in debug , solving problem, see the architecture view, proposing solutions.</li><li>Hands-on experience with industry-standard EDA tools and design flows </li><li>Deep knowledge on PCIe,  axi , DMA, AHB interfaces </li><li>Experience in Verification UVM ,  DDR , flash is a plus</li><li>BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field</li><li>Expertise in high-performance and low-power design techniques</li><li>Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly</li></ul> <h4>Qualifications</h4><ul><li>BE or Master's in Electronics  Engineering,  Electrical Engineering, Computer Engineering, or related field</li><li>10+ years of experience in ASIC development, with a proven track record of leading complex projects</li><li>Advanced knowledge of ASIC design and development, including digital design, verification methodologies, and proficiency in hardware description languages (e.g., Verilog, VHDL)</li><li>Expertise in high-performance and low-power design techniques, with hands-on experience using industry-standard EDA tools</li><li>Strong problem-solving, debugging, and analytical skills to resolve complex technical issues</li><li>Excellent leadership, mentoring, and communication skills, with the ability to guide engineering teams and articulate complex technical concepts</li><li>Understanding of semiconductor industry trends and willingness to work in Bengaluru, India, with occasional travel</li></ul><h4>Additional Information</h4>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at <a href="mailto:jobs.accommodations@sandisk.com">jobs.accommodations@sandisk.com</a> to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.<h4>Experience Level</h4>Senior Level

Chief Engineer

Senior Logic Design EngineerMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.  We are looking for an SOC RTL to PD Engineer to join the team. #azurehwjobs   <h4>Responsibilities</h4><ul><li>Ensure high quality deliverables from RTL to Physical Design</li><li>Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results</li><li>Create, analyze, and maintain timing constraints/SDCs</li><li>Analyze and drive UPF solutions for low power checks</li><li>Drive RTL to Synthesis FEV clean</li><li>Collaborate with RTL and Physical Design team to address design feedback and drive quality</li></ul><h4>Qualifications</h4><ul><li>Required Qualifications:<ul><li>MS with 5+ years of experience or BS with 7+ years of experience. </li><li>At least 5+ years of experience applying digital design principles in SOC and/or IP development. </li><li>Strong Static Timing Analysis background; understanding timing signoff fundamentals. </li><li>Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, and Innovus. </li><li>Experience with timing constraints management and debug tools supporting constraints quality checks, constraints verification, constraints promotion &amp; demotion. </li><li>Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints. </li><li>Understanding in design closure challenges in power and clock domain crossings. </li><li>Understanding reset and FIFO related design requirements.</li></ul></li><li>Preferred Qualifications<ul><li>Experience with FEV and industry standard tools such as Formality and/or Conformal</li><li>Applied understanding of low power design principles. </li><li>Highly Proficient in Verilog/System Verilog coding constructs. </li><li>Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) </li><li>Strong understanding in clock crossing techniques </li><li>Strong understanding in IJPF (Low power intent). </li><li>Ability to write scripts using Perl, TCI, Python etc. </li><li>Familiarity with Industry standard interface protocols is a plus. </li><li>Good verbal and written communication skills. </li></ul></li></ul>Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the <a href="https://careers.microsoft.com/us/en/accommodationrequest" rel="noopener" target="_blank">Accommodation request form</a>. The ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.  Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.<h4>Experience Level</h4>Senior Level

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