Technical Manager - DV

Quest Global is an organization at the forefront of innovation and one of the world’s fastest growing engineering services firms with deep domain knowledge and recognized expertise in the top OEMs across seven industries. We are a twenty-five-year-old company on a journey to becoming a centenary one, driven by aspiration, hunger and humility.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible, possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.

As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:
 

Required Skills (Technical Competency):

• Hands on project experience with verification methodologies UVM
• Domain experience of PCI-e, AMBA, I3C and DDR protocols
• Hands on project experience in verifying SoC with C-SV/UVM based environments.
• Can understand clocking, reset architecture and data flows. Has knowledge of SoC bring-up, bus protocol, register and address map Verification.
• Experience in coverage/assertion driven verification.
• Good knowledge of UNIX shell scripting, Perl and Python scripting
• Experience in writing verification plans and test bench development , simulation, and debugging.
• Proficient with CAE/CAD tools such as schematic capture, simulation, design verification
• Good analytical and problem-solving skills.
• Verifying RTL implementation for complex digital blocks to ensure high quality
• Developing verification strategies for new features, plan volume validation and coverage strategies
• Writing testplan, developing testbenches, coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM
• Working with designers to do coverage analysis and take necessary actions to meet coverage goals
• Integrate VIPs as needed
• Closely work with design teams to drive feature enablement
• Mentor junior engineers on the team