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Silicon Micro-architecture and RTL Lead , Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.</li><li>10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).</li><li>Experience in micro-architecture and design IPs and Subsystems.</li><li>Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).</li></ul> <h4>Preferred qualifications:</h4><ul><li>Experience with scripting languages (e.g., Python or Perl).</li><li>Experience in SoC designs and integration flows.</li><li>Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies..</li><li>Knowledge of high performance and low power design techniques.</li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.<h4>Responsibilities</h4><ul><li>Drive development of Complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization.</li><li>Own micro-architecture and implementation of IPs and subsystems.</li><li>Work with Architecture, Firmware and Software teams to drive feature closure and develop micro-architecture specifications.</li><li>Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Identify and drive Power, Performance and Area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Senior Level

Google India Pvt Ltd

Embedded Systems Engineer

Silicon RTL Design Engineer Networking, Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.</li><li>4 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.</li><li>Experience in micro-architecture and design of IPs and Subsystems.</li><li>Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).</li></ul> <h4>Preferred qualifications:</h4><ul><li>Experience in Networking domain like Packet processing, bandwidth management, congestion control etc.</li><li>Experience with scripting languages (e.g., Python or Perl).</li><li>Knowledge of bus architectures, fabrics/NoC, processor design, or memory hierarchies.</li><li>Knowledge of high performance and low power design techniques. </li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.In this role, you will develop to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.<h4>Responsibilities</h4><ul><li>Own microarchitecture and implementation of IPs and subsystems in the Networking domain.</li><li>Work with design team members to close feature definitions and develop microarchitecture specifications. </li><li>Participate in design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Work on Power, Performance and Area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Mid Level

Senior Engineer - Network modeling (Infowork ICM)<h4>Company Description</h4>Work with Us. Change the World.At AECOM, we're delivering a better world. Whether improving your commute, keeping the lights on, providing access to clean water, or transforming skylines, our work helps people and communities thrive. We are the world's trusted infrastructure consulting firm, partnering with clients to solve the world’s most complex challenges and build legacies for future generations.There has never been a better time to be at AECOM. With accelerating infrastructure investment worldwide, our services are in great demand. We invite you to bring your bold ideas and big dreams and become part of a global team of over 50,000 planners, designers, engineers, scientists, digital innovators, program and construction managers and other professionals delivering projects that create a positive and tangible impact around the world.We're one global team driven by our common purpose to deliver a better world. Join us.<h4>Job Description</h4><ul><li>Contribute to engineering design assignments in a team environment on large-scale project teams.</li><li>Candidate should have minimum 5 years working experience on wastewater modelling for ANZ and UK &amp; I region especially on model calibration &amp; verification.</li><li>Candidate should be well versed with Infoworks ICM hydraulic modelling software.</li><li>Having hands on experience with modeling tools like Water GEMS, SewerGEMS, StormCAD, PCSWMM, HEC-RAS, GeoPak would be advantage.</li><li>Capable for leading the project, coordinating with Lead Office, mentoring juniors and ensuring quality checks.</li><li>Complete design activities to specified standards including earthworks modelling and design, sanitary and storm sewer design, watermain design, grading of roads and drive isles, lot grading, and stormwater management design of ponds and other retention systems.</li></ul><h4>Qualifications</h4><ul><li>Master of Engineering degree (or equivalent education) in an appropriate engineering discipline from an accredited college or university. </li><li>Chartered Engineer (CEng), or Professional Engineer (PE) license or equivalent in the relevant field from any global organization (e.g., Institution of Civil Engineers, UK).</li><li>Highly motivated, hardworking, interpersonal, and enthusiastic team player that is willing to learn and adapt to change.</li><li>US/UK/Canada Experience will be added advantage</li><li>Good communication skills, and ability to work well independently at times.</li><li>Able to see the “bigger picture” and take a birds-eye view of projects</li><li>Confident, with the ability to work either independently or as part of a team.</li><li>Ability to work to deadlines and under pressure.</li><li>Accountability for assigned work.</li><li>Accuracy &amp; precision of work.</li><li>Willingness to learn and develop.</li><li>Excellent written and verbal communication skills</li><li>Strong problem-solving skills</li><li>Enthusiastic and Self-motivated.</li><li>Work well within a multidisciplinary team</li></ul><h4>Additional Information</h4>AECOM provides a wide array of compensation and benefits programs to meet the diverse needs of our employees and their families. We also provide a robust global well-being program. We’re the world’s trusted global infrastructure firm, and we’re in this together – your growth and success are ours too. As an Equal Opportunity Employer, we believe in each person’s potential, and we’ll help you reach yours.#LI-FS1About AECOM AECOM is proud to offer comprehensive benefits to meet the diverse needs of our employees. Depending on your employment status, AECOM benefits may include medical, dental, vision, life, AD&amp;D, disability benefits, paid time off, leaves of absences, voluntary benefits, perks, flexible work options, well-being resources, employee assistance program, business travel insurance, service recognition awards, retirement savings plan, and employee stock purchase plan. AECOM is the global infrastructure leader, committed to delivering a better world. As a trusted professional services firm powered by deep technical abilities, we solve our clients’ complex challenges in water, environment, energy, transportation and buildings. Our teams partner with public- and private-sector clients to create innovative, sustainable and resilient solutions throughout the project lifecycle – from advisory, planning, design and engineering to program and construction management. AECOM is a Fortune 500 firm that had revenue of $16.1 billion in fiscal year 2024. Learn more at aecom.com. What makes AECOM a great place to work You will be part of a global team that champions your growth and career ambitions. Work on groundbreaking projects - both in your local community and on a global scale - that are transforming our industry and shaping the future. With cutting-edge technology and a network of experts, you’ll have the resources to make a real impact. Our award-winning training and development programs are designed to expand your technical expertise and leadership skills, helping you build the career you’ve always envisioned. Here, you’ll find a welcoming workplace built on respect, collaboration and community - where you have the freedom to grow in a world of opportunity. As an Equal Opportunity Employer, we believe in your potential and are here to help you achieve it. All your information will be kept confidential according to EEO guidelines. <h4>Experience Level</h4>Senior Level

Aecom India Pvt Ltd

Senior Network Engineer

Silicon Senior Physical Design Engineer, TPU, Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor’s degree in Electrical Engineering or equivalent practical experience.</li><li>5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.</li><li>Experience with System on a Chip (SoC) cycles.</li><li>Experience in high-performance, high-frequency, and low-power designs.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Master’s degree in Electrical Engineering.</li><li>Experience in coding with System Verilog and scripting with TCL.</li><li>Experience with VLSI design in SoC or multiple-cycles of SoC in ASIC design.</li><li>Experience with layout verification and design rules.</li></ul><h4>About the job</h4>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.<h4>Responsibilities</h4><ul><li>Define and drive the implementation of physical design methodologies.</li><li>Take ownership of one or more physical design partitions or top level.</li><li>Manage timing and power consumption of the design.</li><li>Contribute to design methodology, libraries, and code review. 
</li><li>Define the physical design related rule sets for the functional design engineers.</li></ul><h4>Experience Level</h4>Senior Level

Design Engineer

BIM Manager We’re seeking talented minds&nbsp;who thrive on clarity, collaboration, and long-term impact. Step into work that matters. • Experience - 10+ years What You'll Gain• Projects at grand scale.• Guidance that sharpens your craft.• A culture that balances creativity with growth. Send your updated CV &amp; portfolio&nbsp;now.

Edifice Consultants

Senior Architect

Verification Engineer<h1> </h1>Experience:&nbsp;4-10 YearsJob Descriptions &amp; RequirementsYou should have prior knowledge and experience with UVM verification and UVM environment development Additional responsibilities include:• Help develop test plan definition and development• Micro-architecture design verification, RTL verification, and documentation• Top-level and block-level performance verification, power, and use-case verification; and• Support test program development, chip validation, and chip life until production maturity.• Team Management and Building• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development. Qualifications :• Experience in UVM verification and UVM environment development (must have)• Proficient in test plan definition and testcase development in C/Assembly/System Verilog Expertise

Modernize Chip Solutions

Testing Engineer

Senior Analog Layout Engineer Experience - 4-6 years Please share your CV at <a rel=\"noopener noreferrer\" href=\"mailto:prasad.adakambarribabu@moschip.com\" target=\"_blank\">prasad.adakambarribabu@moschip.com</a>

MosChip Technology Ltd

Electronic Engineer

Platform Board Engineer <ul><li>Lab&nbsp;Support&nbsp;Engineer who&nbsp;can take&nbsp;care&nbsp;of&nbsp;inventory.&nbsp;Need&nbsp;to&nbsp;have basic&nbsp;knowledge&nbsp;of&nbsp;hardware.</li><li>Experience: 5+ Years</li><li>Notice Period: Immediate&nbsp;</li><li>Interview mode: F2F</li></ul> Share your updated resume now.

ACL Digital

Programmer

DFT Engineer <ul><li>Skill: DFT, ATPG, Scan Insertion</li><li>Experience: 4+ years</li><li>Notice Period: Immediate-15 Days</li></ul> Share your updated resume now.

DV Engineer <ul><li>Experience : 4+ years</li><li>Notice period : immediate to 30 days</li></ul> Share your updated resume now.

Assistant Design Engineer

Technical Architect Mandatory Skills:<ul><li>Frontend: UI with Angular or React</li><li>Backend: Java &amp; Python</li><li>Database: Strong expertise in database design &amp; optimization</li><li>Architecture: End-to-End application design (Frontend + Backend + DB)</li></ul> <ul><li>Experience: 10–12 Years</li><li>Immediate Joiners Preferred</li></ul> Share your resume now with Subject: Technical Architect – &lt;location&gt;

Kairos Technologies

Architect

ROS Engineer Skills - C++ / Python, ROS, Linux, RTOSExperience - 2+ year Please Note:We will connect only with candidates whose profiles closely match our requirements and budget.

Delhivery

RO System Specialist

WLAN Developer Key Responsibilities<ul><li>Extensive experience in WLAN Driver development.</li><li>Exposure to Android is good to have</li><li>Proficiency in programming languages such as C/C++ for embedded systems.</li><li>Knowledge of WLAN protocols (802.11a/b/g/n/ac/ax) and standards.</li><li>Familiarity with ARM Based chipsets, drivers, and WLAN software development kits.</li><li>Strong problem-solving skills and ability to troubleshoot complex WLAN issues.</li><li>Effective communication and collaboration skills in a team environment.</li></ul> Requirements<ul><li>Bachelor’s or master’s degree in computer science, Electrical Engineering, or a related field.</li><li>3 to 6 years of experience in WLAN or embedded systems.</li><li>Strong problem-solving and analytical skills.</li></ul>

Eximietas Design

Network Engineer

Design Verification Engineer <ul><li>Skills - Python, ARM SoCs, Linux, RTOS, System-level development, validation, automation.</li><li>Experience - 3–5 years</li><li>Notice Period: 0–30 Days</li></ul> Send your updated CV to <a rel=\"noopener noreferrer\" href=\"mailto:anushakonda@mirafra.com\" target=\"_blank\">anushakonda@mirafra.com</a>

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