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Senior Analog Layout Engineer Experience - 4-6 years Please share your CV at <a rel=\"noopener noreferrer\" href=\"mailto:prasad.adakambarribabu@moschip.com\" target=\"_blank\">prasad.adakambarribabu@moschip.com</a>

MosChip Technology Ltd

Electronic Engineer

Platform Board Engineer <ul><li>Lab&nbsp;Support&nbsp;Engineer who&nbsp;can take&nbsp;care&nbsp;of&nbsp;inventory.&nbsp;Need&nbsp;to&nbsp;have basic&nbsp;knowledge&nbsp;of&nbsp;hardware.</li><li>Experience: 5+ Years</li><li>Notice Period: Immediate&nbsp;</li><li>Interview mode: F2F</li></ul> Share your updated resume now.

ACL Digital

Programmer

DFT Engineer <ul><li>Skill: DFT, ATPG, Scan Insertion</li><li>Experience: 4+ years</li><li>Notice Period: Immediate-15 Days</li></ul> Share your updated resume now.

Testing Engineer

DV Engineer <ul><li>Experience : 4+ years</li><li>Notice period : immediate to 30 days</li></ul> Share your updated resume now.

Assistant Design Engineer

Technical Architect Mandatory Skills:<ul><li>Frontend: UI with Angular or React</li><li>Backend: Java &amp; Python</li><li>Database: Strong expertise in database design &amp; optimization</li><li>Architecture: End-to-End application design (Frontend + Backend + DB)</li></ul> <ul><li>Experience: 10–12 Years</li><li>Immediate Joiners Preferred</li></ul> Share your resume now with Subject: Technical Architect – &lt;location&gt;

Kairos Technologies

Architect

ROS Engineer Skills - C++ / Python, ROS, Linux, RTOSExperience - 2+ year Please Note:We will connect only with candidates whose profiles closely match our requirements and budget.

Delhivery

RO System Specialist

WLAN Developer Key Responsibilities<ul><li>Extensive experience in WLAN Driver development.</li><li>Exposure to Android is good to have</li><li>Proficiency in programming languages such as C/C++ for embedded systems.</li><li>Knowledge of WLAN protocols (802.11a/b/g/n/ac/ax) and standards.</li><li>Familiarity with ARM Based chipsets, drivers, and WLAN software development kits.</li><li>Strong problem-solving skills and ability to troubleshoot complex WLAN issues.</li><li>Effective communication and collaboration skills in a team environment.</li></ul> Requirements<ul><li>Bachelor’s or master’s degree in computer science, Electrical Engineering, or a related field.</li><li>3 to 6 years of experience in WLAN or embedded systems.</li><li>Strong problem-solving and analytical skills.</li></ul>

Eximietas Design

Network Engineer

Consultant - Electromechanical Engineer Capgemini is Hiring below role: Designation: ConsultantSkill: Electromechanical Engineer Experience: 4–6 Years ﻿If interested Send your CV: Mention the Role Title in the subject line.

Capgemini

Technical Consultant

Design Verification Engineer <ul><li>Skills - Python, ARM SoCs, Linux, RTOS, System-level development, validation, automation.</li><li>Experience - 3–5 years</li><li>Notice Period: 0–30 Days</li></ul> Send your updated CV to <a rel=\"noopener noreferrer\" href=\"mailto:anushakonda@mirafra.com\" target=\"_blank\">anushakonda@mirafra.com</a>

Mirafra Software Technologies Pvt Ltd

Sr Verification Engineer<h1> </h1>Experience:&nbsp;4-10 YearsAs a Verification Engineer, you will play a crucial role in the development of next-generation Storage Networking ASICs. Your primary responsibilities will include:• Develop a detailed micro-architecture for both module-level and system-level test benchesVerification Micro-Architecture &amp; Documentation:• Produce comprehensive documentation outlining verification strategies and approaches.Firmware and Hardware Co-Simulations:• Conduct co-simulations to ensure seamless integration and functionality between firmware and hardware components.Test Plan Development:• Create detailed test plans, outlining methodologies and criteria for effective verification.Test Bench Coding and Test Writing:• Develop and code test benches, and write tests to validate module-level and system-level functionalities.Debugging:• Troubleshoot and resolve simulation failures at both module and system levels.RTL Code Coverage Analysis and Enhancements:• Analyze RTL code coverage to identify gaps and propose enhancements to improve verification coverage.Scripting for Automation:• Develop scripts to automate various aspects of the verification process, enhancing overall productivity and efficiencyValidation Support:• Assist in FPGA and ASIC validation processes, which includes analyzing Ethernet and PCIe traces and detailed hardware logging during system operation Requirement:• Graduation with 3+ years of hands-on code development experience• A degree in EE, CE, or CS

Modernize Chip Solutions

Design Verification Engineer This job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job OverviewWe are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description<ul><li>Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.</li><li>Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM</li><li>Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.</li><li>Analyze and implement System Verilog assertions and coverage (code, toggle, functional).</li><li>Provide mentorship and technical guidance to junior verification engineers.</li><li>Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.</li><li>Ensure verification signoff criteria are met and documentation is comprehensive.</li><li>Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.</li><li>Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.</li><li>Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.</li></ul> Qualifications<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>Master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design Verification.</li><li>Expertise in UVM (Universal Verification Methodology) and System Verilog.</li><li>Prior experience working on IP level and SOC level verification projects.</li><li>Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).</li><li>Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.</li><li>Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.</li><li>Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Proficiency in scripting languages such as shell, Makefile, and Perl.</li><li>Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.</li><li>C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.</li></ul>

RTL ENGINEER Experience: 4+ YearsThis job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job Description Required<ul><li>Solid RTL coding experience including</li><li>Microarchitecture of design</li><li>System Verilog and Verilog coding using provided coding styles.</li><li>Understanding of SDC</li><li>Understanding STA reports and how to adjust RTL accordingly.</li><li>Designing for error cases and debug of IP</li><li>Understanding of CDC logic</li><li>Knowledge of lint rules and exceptions</li><li>Design and use of block level simulations to bring up IP.</li><li>Knowledge of AMBA buses and when to use them.</li></ul> Job Description Preferred<ul><li>Experience&nbsp;leading small design team.</li><li>C coding / Firmware skills</li><li>Knowledge on common processor architectures&nbsp;(ARM, RiscV)</li><li>FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA.</li><li>Lab brings up experience, scripting.</li><li>Relevant tool experience such as: Socrates, Core Consultant in addition&nbsp;to standard simulation tools (xcellium, vcs, etc)</li><li>Emulation experience&nbsp;(Zebu, Palladium, etc)</li><li>Board knowledge, component selection, probing, debug.</li><li>JTAG debugging experience (Coresight, Lauterbach, etc).</li><li>Low power design techniques</li></ul> Qualifications<ul><li>E./B.Tech. degree at minimum.</li></ul>

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